This paper presents the design of a low-cost programmable controller integrated circuit (IC) for general power electronics applications. The architecture of the programmable controller IC consists of 10-bit ADC and DAC, programmable counter array (PCA), which is configured to function as PWM, and a control unit (processor) for regulation. The processor unit is configured as digital compensator, through fewer program steps to perform accurate compensation on the voltage control loop of the converter system. Limit-cycle oscillation is minimized through inclusion of a sufficiently low integral gain term in the control law. A hybrid control method is first used to control the input voltage and current waveforms to achieve a unity power factor correction. It is observed that the programmable converter achieves the high efficiency power conversion. The conversion efficiency of the digital controlled boost converter is 91% with a 0.8% ripple voltage performance. While in power factor correction (PFC) circuit application, the power factor and output ripple voltage of converter are 0.995 and 0.93%, respectively. The chip is implemented with TSMC 0.25 um CMOS process.

A method for the fabrication of $n$ -type porous silicon $\left(n\text{‐}\mathrm{PS}\right)$ is developed. The Hall effect is applied in the fabrication process. The majority carriers in $n$ -type Si (electrons) are swept down by the Lorentz force. Enough holes continuously appear on the surface layer to participate in chemical reaction during the etching process. Illumination sources are not necessary in this method. Therefore, no illumination limit has to be concerned in the formation of deep PS layer. The morphology, porosity, and photoluminescence of the $n\text{‐}\mathrm{PS}$ prepared by the proposed method are investigated. Strong visible photoluminescence emissions are demonstrated on $n\text{‐}\mathrm{PS}$ at about $650\mathrm{nm}$ .

Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nm Al ₂ O ₃ interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability $\sigma /\mu $ (standard deviation/mean) of any resistance state was 28.7% in reset-stop voltage control methods. The multilevel switching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al ₂ O ₃ barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.

A new approach for the fabrication of n-type porous silicon layer is proposed. A hole-rich p-layer is arranged underneath the n-layer, and the np-junction is under forward biased condition in the etching process. Therefore sufficient holes can drift straight-upward and pass across the np-junction from p-region to n-region to participate in electrochemical reaction during the etching process with an unfailing supply. Illumination is an optional hole-supplier in this approach, so the problem of illumination-depth limitation can be overcome. Strong visible photoluminescence emissions are demonstrated on the hole-poor n-type porous layer at about 650 nm.

The design of a 5 GHz phase-locked loop (PLL) with a phase-adjusting function is presented. The voltage-controlled delay line (VCDL) is proposed to adjust the feedback signal phase by an externally controlled voltage. The output phase difference of multi-PLLs can be shifted from 0 $^{\circ}$ to 98.6 $^{\circ}$ , when the propagation delay of VCDL is 0.41 and 4.75 ns, respectively. The proposed PLL was fabricated in TSMC 0.18- $\mu $ m CMOS process and supplied at 1.8 V with a power dissipation of 16.38 mW. The locking time is less than 2 $\mu $ s under the different controlled-voltage ranges of VCDL.