This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

This paper presents a simple capacitor mismatch calibration in SAR ADCs, which is in foreground and on chip. Capacitor errors are extracted based on output histogram under a triangular input signal generated on chip and compensated by tuning capacitors with a calibration DAC. A novel one-by-one strategy can simplify the extraction by isolating the individual contribution of each capacitor error. The proposed calibration needs no computation and is validated with a 10-bit 100MS/s SAR ADC. Size of the ADC core including calibration system is only 90μm×97μm. Measurement results show effectiveness of the proposed calibration.

This paper presents an 8-bit 1.6GS/s successive-approximation-register analog-to-digital converter (SAR ADC) with alternate comparators. To enhance dynamic performance and speed, a dither-based background relative offset calibration and a fast SAR logic are proposed. In the background calibration, the least significant bit (LSB) can indicate the polarity of the relative offset between comparators after injecting dither into the input, facilitating calibration without extra phase. The fast SAR logic, which includes a trigger logic and a digital-to-analog converter (DAC) control logic, features a 3-logic-gate delay, resulting in a reduced bit duration. These techniques are validated by a prototype 8-bit SAR ADC in 28 nm CMOS technology, exhibiting the highest speed (1.6 GS/s) and smallest area (0.0008 mm2) among single-channel 8-bit SAR ADC. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) improves from 31.6 dB to 43.6 dB, while the spurious-free dynamic range (SFDR) improves from 38.7 dB to 58.3 dB after offset calibration. It consumes 5.73 mW from 1-V supply, yielding a Walden FoM of 29.0 fJ/conv-step.

This brief presents a 14-bit 4 GS/s time-interleaving ADC design using two interleaved sub-ADCs. The sub-ADC achieves 2 GS/s conversion rate in 28nm CMOS technology and uses pipelined structure to have high resolution at the same time. In the adopted sample-and-hold amplifier-less (SHA-less) pipeline, a comparator-based correction method is proposed to solve the associated aperture error in the frontend stage where input is sampled at the latch node. By tunning the path bandwidth, rather than using delay line in comparator clock path, the output spreading related to aperture error is reduced by the proposed tunning method to offset-limited level up to 4 GHz input frequency. The modified reference buffer in the ADC reuses the existing transconductance and improves its power efficiency when driving the pipeline stages. Buffers and digital calibrations are implemented on-chip to help wideband high-speed operation and to correct non-idealities in analog circuits. The fabricated ADC chip achieves 59.7 dB SNDR, 60.3 dB SNR and 69.3 dBc SFDR at 1.95 GHz input frequency. The input bandwidth is above 5 GHz. ADC power consumption is 782 mW, resulting in 247.8 fJ/conv.-step FoMW and 153.7 dB FoMS.

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip's total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm ² and is implemented in a 130nm CMOS process.