An emission-stable nanoscale air channel diode, consisting of two asymmetric flat emitters and a sub-100 nm air channel, is proposed and fabricated by a low-cost and IC compatible BOE Etching Process.

An ultra-low quiescent current resistor-less power on reset circuit is presented in this paper. The circuit is used in energy harvesting systems to change boost converter from startup state to PWM modulation state. It integrates power on reset (POR) and brown out detection (BOD) functions without resistors or bandgaps overhead. Dual threshold detection (DTD) technology is used instead of a large size delay cell in generation of pulse signals. The circuit has been implemented in a 0.13μm standard CMOS technology. The active area and the quiescent current of the circuit are 154.4μm × 26.8μm and about 1nA, respectively. Ultra-low quiescent current and small area make the proposed circuit suitable to be applied in low power applications like energy harvesting and beyond.

The thermoelectric generator (TEG) stands out among many energy harvesters due to its simple structure, small size, rich thermal energy, and the absence of pollution and noise. However, previous studies have rarely probed into the influence of TEG internal resistances on extracting maximum power from TEGs, and the tracking of efficiency is limited. By analyzing the relationship between the tracking efficiency and the TEG internal resistances, a time exponential rate perturbation and observation (P&O) technology is proposed to achieve maximum power point tracking (MPPT) for a wide resistance range of the TEG. Using the time exponential rate P&O, the MPPT circuit observed the power change by comparing the positive-channel metal-oxide semiconductor (PMOS) on-time and perturbs the power by adjusting the negative-channel metal-oxide semiconductor (NMOS) on-time exponentially. The MPPT circuit was implemented in a 110 nm complementary metal-oxide semiconductor (CMOS) process. The tracking efficiency maintained a high level from 98.9 to 99.5%. The applicable range of the TEG resistance was from 1 to 12 Ω, which reflects an enhancement of at least 2.2 times.

Since spiking neural networks can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale spiking neural networks requires a simple and versatile silicon neuron model framework. In this paper, a spiking neuron circuit as the core device of spiking neural networks is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas-Niebur mathematical model is adopted. The improved Mihalas-Niebur model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

Phase change memory (PCM) is considered one of the most promising next-generation non-volatile memory types for storage-class memory due to its many advantages, including ultrafast programming, long data retention, high storage density, low power consumption, and compatibility with standard CMOS processes. However, in conventional PCM programming circuits, the first programming operation after power-on suffers from a slow rise time in the programming pulse due to the lack of bias voltage pre-charging in the current source circuit, which leads to reduced consistency in the programming of phase change cells. In this study, we developed two solutions to address the issue associated with conventional PCM programming circuits. We also analyzed conventional programming circuit schemes and designed a PCM programming circuit with improved speed using the SMIC 40 nm CMOS process. The results demonstrated that compared with conventional programming circuits, the PCM programming circuit with improved speed reduced the rise time of SET pulses from 29.6 ns to 7.3 ns and the rise time of RESET pulses from 13.6 ns to 3.1 ns. In addition, it improved the consistency of the programming phase change cells and reduced the power consumption from 11.93 mW to 10.35 mW.

The 3-D vertical array architecture is considered to be a promising technology for emerging nonvolatile memories. But in 3-D vertical emerging nonvolatile memories, planar parasitic elements, vertical parasitic elements, and the sneak currents of the half-selected memory cells result in the delay of the read operation and read errors. This paper refers to the case of the 3-D vertical resistive switching random access memory (RRAM) technology. A read scheme, the memory core design, and the read path are proposed or analyzed. The factors that affect the read operation are concluded. A changing-reference parasitic-matching sensing circuit is, therefore, proposed. In the proposed circuit, the reference side and the read side share similar sneak currents and read paths. Simulated in a 40-nm CMOS process, the sensing time of 128-Mb 3-D vertical RRAM is 8.54 ns compared to the conventional 34.26 ns. Monte Carlo simulations show a 130.21-ns worst sensing time compared to the conventional 401.95 ns. The read errors are reduced by 100% and 95.31% under the regular and the worst RRAM resistance, respectively.