Two-dimensional materials have garnered interest from the perspectives of physics, materials, and applied electronics owing to their outstanding physical and chemical properties. Advances in exfoliation and synthesis technologies have enabled preparation and electrical characterization of various atomically thin films of semiconductor transition metal dichalcogenides (TMDs). Their two-dimensional structures and electromagnetic spectra coupled to bandgaps in the visible region indicate their suitability for digital electronics and optoelectronics. To further expand the potential applications of these two-dimensional semiconductor materials, technologies capable of precisely controlling the electrical properties of the material are essential. Doping has been traditionally used to effectively change the electrical and electronic properties of materials through relatively simple processes. To change the electrical properties, substances that can donate or remove electrons are added. Doping of atomically thin two-dimensional semiconductor materials is similar to that used for silicon but has a slightly different mechanism. Three main methods with different characteristics and slightly different principles are generally used. This review presents an overview of various advanced doping techniques based on the substitutional, chemical, and charge transfer molecular doping strategies of graphene and TMDs, which are the representative 2D semiconductor materials.

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n⁺-p-n⁺ as in the conventional structures. The proposed topology achieves an elongated retention time (Tret) with larger physical barrier thickness (ToxPB) and wider barrier offset length (LBO) due to a reduction in band-to-band tunneling (BTBT) (during hold ``0'') and recombination (during hold ``1''). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 10¹⁹ cm⁻³ at 27 °C and 85 °C, respectively, with gate length (Lg) of 100 nm at small drain bias (VDS) of 1 V during write ``1.'' Results demonstrate a better gate length scalability and a retention time of ~4 ms at Lg of 15 nm with thinner Si channel thickness under the gate (TSi) and thicker ToxPB. In addition, the effect of temperature on retention time has been analyzed. With optimized ToxPB at Lg = 100 nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.

In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( T _ret ) and larger sensing margin (SM). The designed 1T DRAM achieves T _ret ~ 330 and ~ 200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write “1”) and energy ( 2.16×10 ^-15 J for read “1” and 1.5×10 ^-17 J for read “0” operations). Furthermore, it is revealed that low- κ spacer has an effect of increasing T _ret in the device.

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware.

Hardware-oriented neuromorphic computing is gaining great deal of interest for highly parallel data processing and superb energy efficiency, as the candidate for replacement of conventional von Neumann computing. In this work, a novel synaptic transistor constructing the neuromorphic system is proposed, fabricated, and characterized. Amorphous indium-gallium-zinc-oxide ( α-IGZO) and Al ₂ O ₃ are introduced as the channel and gate dielectric materials, respectively. Along with the high functionality and low-temperature processing viability, geometric peculiarity featuring extended gate structure improves the performances of the proposed transistor as synaptic component in the neuromorphic system. The insight into the substantial effect of optimal device structure design on energy efficiency is highlighted.