We demonstrate ferroelectric (FE) memory transistors on a crystalline silicon channel with endurance exceeding 10 ¹⁰ cycles. The ferroelectric transistors (FeFETs) incorporate a high- $\kappa $ interfacial layer (IL) of thermally grown silicon nitride (SiN _x ) and a thin 4.5 nm layer of Zr-doped FE-HfO ₂ (HZO) on a ~30 nm silicon on insulator (SOI) channel. The device shows a ~1V memory window (MW) in a DC sweep of just ± 2.5V, and can be programmed and erased with voltage pulses of $\text {V}_{\text {G}}= \pm \,\,3\text{V}$ at a pulse width of 250 ns. The device also shows very good retention behavior. These results indicate that appropriate engineering of the IL layer could substantially improve FeFET device performance and reliability.

In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

Ferroelectric field-effect transistors (FeFETs) based on HfO ₂ are promising for low-power and high-speed non-volatile memory devices. However, most reported FeFETs show limited write endurance and significant read-after-write delay due to parasitic charge trapping. Here we show that n-type FeFETs with SiN _x interfacial layer and high write endurance also exhibit immediate read-after-write behavior due to negligible charge trapping. This overcomes one of the major challenges faced by FeFET technologies today.

We investigate the characteristics of a synaptic imitation device using a thin-film transistor (TFT)-type NOR flash memory cell with a half-covered floating gate. The long-term potentiation (LTP) and long-term depression (LTD) required for the operation of the spike-timing-dependent plasticity (STDP) algorithm are implemented using the proposed pulse scheme. Unsupervised learning is successfully demonstrated by applying the STDP learning rule through software MATLAB simulation reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory array. We present the learning and recognition processes of 28 × 28 MNIST handwritten digit patterns. First, STDP learning in a single-neuron string (784 × 1 ) is investigated, after which STDP learning is demonstrated in a multineuron array (784 × 10) with a lateral inhibition function to demonstrate the ability of multipattern learning and recognition. Meanwhile, we investigate the key factors of STDP unsupervised learning. Finally, an approach is suggested to implement a hardware neural network using the conventional CMOS technology for STDP unsupervised learning as a visual pattern recognition system.

In this study, the oxygen flow rate (OFR) dependence of negative bias illumination stress (NBIS) and positive bias stress (PBS) in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) devices was investigated. Unlike in previous studies, our study simultaneously considered and analyzed the bias stress-induced degradation mechanisms by charge trapping and defect creation. NBIS and PBS instability were measured according to the OFR splits of bottom-gate (BG) IGZO TFTs and the behavior of full subgap range density of states (DOS) was experimentally tracked with especial emphasis on deep-level oxygen vacancy ( ${V}_{\text {O}}$ ) peak. It was found that the observed DOS variation was consistent with the ${V}_{\text {O}}$ ionization model during NBIS. In addition, the threshold voltage shift by charge trapping ( ${\Delta } {V}_{\text {T,CT}}$ ) and the threshold voltage shift by defect creation, i.e., change of DOS, ( ${\Delta } {V}_{\text {T,DOS}}$ ) were separated and extracted through the subthreshold slope decomposition method. After NBIS, the threshold voltage shift ( ${\Delta } {V}_{\text {T}}$ ) was composed of a component by charge trapping and a component with the ionization of ${V}_{\text {O}}$ . After PBS, ${\Delta } {V}_{\text {T}}$ was dominated by a component arising due to charge trapping. Fitting through the stretched exponential function (SEF) was performed for each separately extracted ${\Delta } {V}_{\text {T}}$ , and the activation energy for each ${\Delta } {V}_{\text {T}}$ was extracted using the inverse Laplace transform method through the extracted ${\Delta } {V}_{\text {T0}}$ , $\tau $ , and $\beta $ . Activation energy by charge trapping and DOS was extracted from NBIS and PBS, respectively. As a result of simultaneously considering the two degradation mechanisms, the extracted activation energy was located between the previous values. Experimentally extracted sets of DOS-specific parameters before and after bias stress were applied to technology computer-aided design (TCAD) simulations. Accurate reproduction of TFT current–voltage ( ${I}$ – ${V}$ ) curves before and after bias stress and recovery suggests that the methodology and parameter set used in this study are reasonable and potentially useful for a more robust and systematic analysis of the bias stress-induced instability in a-IGZO BG TFTs.