A complementary metal–oxide–semiconductor (CMOS) detector array is proposed to improve the sub-terahertz imaging resolution for objects in the conveyor belt system. The image resolution is limited to the implemented configuration, such as the wide spacing in the detector array, the high conveyor belt speed, and the slow response of the signal conditioning block. The proposed array can improve the image resolution in the direction perpendicular to the movement of the belt, which is determined by the size and interval of the detector pixel, by configuring the array into two replaceable columns located at the misaligned horizontal positions. Replaceable detector unit pixels are individually attached to the motherboard after measuring and evaluating the detection performance to construct the proposed array. The intensities of 32 detector pixels placed under the conveyor belt with a width of 160 mm were initially calibrated in every image, including the beam pattern of 0.2 THz signals generated from the gyrotron. The image resolution of the perpendicular direction obtained from the proposed array was measured to be approximately 5 mm at a conveyor belt speed of 16 mm/s, demonstrating a 200% improvement in resolution compared to the conventional linear array under the same conditions.

A CMOS detector with a concurrent mode for high-quality images in the sub-terahertz region has been proposed. The detector improves output-signal coupling characteristics at the output node. A cross-coupling capacitor is added to isolate the DC bias between the drain and gate. The detector is designed to combine a 180° phase shift based on common source operation and an in-phase output signal based on the drain input. The circuit layout and phase shift occurring in the cross-coupled capacitor during phase coupling are verified using an EM simulation. The detector is fabricated using the TSMC 0.25-μm mixed-signal 1-poly 5-metal layer CMOS process, where the size, including the pad, is 1.13 mm × 0.74 mm. The detector IC comprises a folded dipole antenna, the proposed detector, a preamplifier, and a voltage buffer. Measurement results using a 200-GHz gyrotron source demonstrate that the proposed detector voltage responsivity is 14.13 MV/W with a noise-equivalent power of 34.42 pW/√Hz. The high detection performance helps resolve the 2-mm line width. The proposed detector exhibits a signal-to-noise ratio of 49 dB with regard to the THz imaging performance, which is 9 dB higher than that of the previous CMOS detector core circuits with gate-drain capacitors.

An envelope-detection-based signal preprocessing technique is proposed to robustly enhance the signal-to-noise ratio (SNR) in subterahertz (sub-THz) imaging systems. Conventional peak-based amplitude extraction is highly sensitive to high-frequency noise and detector- induced direct-current (DC) offset drift, resulting in unstable intensity estimation and degraded image uniformity. The proposed approach directly extracts the signal envelope from the sampled waveform, providing noise-resilient and drift-tolerant amplitude detection without computationally intensive post-processing. The method is implemented in a sub-THz imaging platform employing a 0.18-μm CMOS plasmonic detector. Experimental results from 0.15-THz raster-scanned images of a metallic test target demonstrate an SNR improvement of approximately 9 dB compared with peak detection, along with enhanced spatial uniformity and image fidelity. Owing to its low computational overhead, the proposed technique is well suited for real-time and embedded sub-THz imaging applications.

A scalable and interchangeable 8×8 CMOS detector array module is proposed for sub-terahertz imaging systems. The architecture supports expansion from a 2×2 detector IC to 4×4 and 8×8 configurations. Each 2×2 detector IC, featuring an integrated antenna, is mounted on a daughterboard. In the 8×8 array configuration, four daughterboards are arranged on a motherboard, with the detector ICs placed at the corners of the daughterboards and evenly distributed at the center of the motherboard. Interconnections for biasing and output readout are implemented via multilayer transmission lines routed between uniformly spaced ICs. The detector ICs, fabricated using a 0.25-μm CMOS process, demonstrated a mean voltage responsivity of 214.9 kV/W with a standard deviation of 46.6 kW/W and a noise equivalent power of 21.7 pW/√Hz with a standard deviation of 4.8 pW/ √Hz at 0.2 THz, across a 36×36 mm² 8×8 array. Raster-scanned imaging at intervals of 10, 8, 6, 4, 2, and 1 mm yields an image correlation index of 0.77, enabling sub-wavelength pattern recognition down to 1 mm.

An $LC$ -enhanced plasmonic detector for sub-terahertz (sub-THz) imaging is presented, fabricated using a standard 0.18- $\mu $ m CMOS process. The detector adopts a differential topology with cross-coupled capacitors and incorporates drain inductors, which form $LC$ paths that enhance high-frequency signal transfer and increase the drain impedance. This configuration strengthens fundamental coupling while attenuating low-frequency noise components. In addition, the inductors provide an impedance-loading effect, increasing the drain impedance, which boosts both the output voltage swing and voltage responsivity. The fabricated detector occupies a compact die area of $0.79\times 0.70$ mm². Measurement results demonstrate a peak voltage responsivity of 1561 kV/W and a minimum noise equivalent power of 11.6 pW/ $\surd $ Hz at 150 GHz. Sub-THz imaging experiments achieve a signal-to-noise ratio of 29.2 dB, validating the effectiveness of the detector for high-resolution, low-noise passive imaging applications.