The structural, chemical, and electrical properties of amorphous indium gallium zinc oxide (a-IGZO) films by magnetron sputtering and atomic layer deposition (ALD) were investigated where both a-IGZO films had a comparable cation composition. The ALD-derived a-IGZO film exhibited the higher atomic packing density, the effective suppression of trap-like oxygen vacancy defect (Vₒ), and the enhancement in the hybridization of the sp orbital of In, Ga, and Zn cations compared to those of the sputtered a-IGZO film. Hence, a significant improvement in terms of the field-effect mobility was observed for the thin-film transistors with an In0.50Ga0.34Zn0.16O channel by ALD (36.6 cm²/V· s) compared to that of the sputtered In0.48Ga0.38Zn0.14O transistor (20.1 cm²/V· s); the Ion/off ratios for both were ~ 10⁷. Simultaneously, the gate bias stress stability and photobias stress stability were also improved for the IGZO transistors with an ALD-derived channel, which can be explained by its reduced trap-like Vₒ density.

We propose a novel structure to solve the hole erase problem of Indium-Gallium-Zinc-Oxide (IGZO) channels. The proposed structures are an IGZO-nitride-P filler (INP) structure and an IGZO-P filler (IP) structure. In the simulations using both structures, stable operation and erase efficiency can be achieved in an INP structure when the nitride barrier thickness is 7 nm. The erase performance achieved exceeds that of the polysilicon channel under the same conditions. Conversely, if the nitride thickness exceeds 8 nm, the read operation becomes unstable. Therefore, nitride thickness is an important parameter in the operation of an INP structure, and its maximum value is 7 nm. For improving upon this INP structure, the nitride was removed to create an IP structure, in which, leakage currents could be limited by reducing doping concentration. In particular, such an IP structure showed that the maximum erase performance (2 ms) of the polysilicon channel can only be achieved at 2.3 μs, and then the erase operation can continue. This result is due to lack of electron accumulation in the channel and their ability to move quickly through the filler directly connected to the IGZO channel. As a result, both proposed structures have shown that low erase performance can be overcome without sacrificing the excellent leakage current blocking characteristics of IGZO material.

Three-dimensional crossbar technology has been of great significance for realizing high density and multiple terabytes of data storage in memory devices. However, to further scale down the size of memory devices, a selector exhibiting nonlinear electrical properties should be in series with a memory layer in case of unwanted sneak current disturbance. Conventional selectors usually utilize a complicated multilayer structure to realize the high nonlinearity of current, which might be incompatible with certain manufacturing processes or limit the scalability of memory. Herein, we propose a simple heterojunction diode using an n-type oxide semiconductor, specifically, InGaZnO₄(IGZO), and a p-type phase change material (PCM), specifically, N-doped Cr₂Ge₂Te₆(NCrGT), to realize self-selective performance. The electrode/IGZO/NCrGT/plug-electrode structure with an IGZO/NCrGT pn diode and NCrGT/plug-electrode Schottky diode can realize bidirectional, self-selective phase change random access memory (PCRAM) for either amorphous or crystalline NCrGT. The approximate equilibrium energy band diagrams for the IGZO/NCrGT pn junction and the IGZO/NCrGT/W hybrid junction were proposed to explain the possible conduction mechanism. We demonstrated that hybrid diode-type PCM memory exhibits both selectivity and resistive switching characteristics. The present findings offer new insight into selector technology for PCM.

This paper presents a process for the fabrication of vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays using glass reflow and anodic bonding techniques. Silicon through-wafer interconnects have been investigated by the glass reflow process. Then, the patterned silicon-glass reflow wafer is anodically bonded to an SOI (silicon-on-insulator) wafer for the fabrication of CMUT devices. The CMUT 5 × 5 array has been successfully fabricated. The resonant frequency of the CMUT array with a one-cell radius of 100 µm and sensing gap of 3.2 µm (distance between top and bottom electrodes) is observed at 2.84 MHz. The Q factor is approximately 1300 at pressure of 0.01 Pa.

In this work, we present the results of an investigation of the impact of the stress on a poly-silicon channel induced by the neighboring layers in three-dimensional vertical NAND (3D V-NAND) flash memories. Using 3D process simulations, we confirmed the distributions of the residual stress after each process step in the cross-section of a NAND flash unit cell. To investigate the impact of the stress on the poly-silicon channel, we also studied the residual stress after changing the intrinsic stresses of the oxide-nitride-oxide (ONO) layer and the tungsten layer used as a gate. We found that the amplitude of the residual stress in the applied layer became larger as the intrinsic stress increased. In addition, the intrinsic tensile/compressive stresses in the outer layers affected the residual stresses of the previously deposited layers in an opposite nature of the stresses. The cylindrical poly-silicon channel was influenced by the intrinsic stresses of the oxide layers adjacent to the nitride and the tungsten films, with the intrinsic stress of the tunnel oxide having the greater effect on the residual stress in the channel. Because such stresses affect the electrical properties of the devices, optimized deposition conditions are required to control them. Such conditions would aid in improving the performances of 3D NAND flash memories.