In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors. To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized. We report for the first time on the observation of a positive temperature dependence, i.e., a higher temperature leads to a higher gate breakdown voltage. Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction. Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement. This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs.

High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the ${C}$ – ${V}$ behavior depends on the different processing conditions of the p-GaN gate. Second, a two-junction capacitor model considering a series connection of the Schottky metal/p-GaN junction capacitor and the AlGaN barrier capacitor is proposed to explain this ${C}$ – ${V}$ behavior. Based on this model, the junction capacitance has an influence on the total capacitance value under a high gate bias due to the Schottky metal/p-GaN junction. Furthermore, the Mg-concentration and hole density can be extracted. The extracted hole density is consistent with the results obtained by Hall measurements.

The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole-Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN ``p-i-n'' diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at t₁%=10 years.

An analytical model for the calculation of the threshold voltage for enhancement-mode (E-mode) p-(Al)GaN high-electron-mobility transistors (HEMTs) is presented. The ON-state behavior (at low output voltages) of both p-GaN HEMTs and p-AlGaN HEMTs--including the gate injection transistor--are discussed in detail, and closed expressions for the threshold voltage VT of both devices are deduced. It is found that the threshold voltage values for both devices are close to one another, and that there is an ideal upper limit when the p-type doping in the AlGaN gate is perfectly tailored, yielding more positive threshold voltages. This ideal case might be difficult to realize technologically, but can serve as a benchmark for the VT of p-(Al)GaN HEMTs.

We report the first comprehensive research about GaN power integrated circuits (ICs) on GaN-on-SOI (silicon-on-insulator). Specific stepped (Al)GaN superlattice buffer and highly robust deep trench isolation are developed. Various components including HEMT, metal-insulator-metal (MIM) capacitor, Schottky barrier diode (SBD), two-dimensional electron gas (2DEG) resistor, and resistor-transistor logic (RTL) are co-integrated, compatible with the p-GaN technology. Based on these achievements, 200 V GaN HEMT with integrated driver shows an extraordinary switching performance. A 48V-to-1V single-stage buck converter is realized using a GaN half-bridge with integrated on-chip drivers. Further, an all-GaN buck converter containing a smart control pulse-width modulation (PWM) circuit, dead-time control, drivers, and half-bridge is successfully designed using the GaN IC platform process design kit (PDK).