The Shack-Hartmann wavefront sensor (SHWS) is an essential tool for wavefront sensing in adaptive optical microscopes. However, the distorted spots induced

With the platforms of running deep neural networks (DNNs) move from large-scale data centers to handheld devices, power emerge as one of the most significant obstacles. Voltage scaling is a promising technique that enables power saving. Nevertheless, it raises reliability and performance concerns that may undesirably deteriorate NNs accuracy and performance. Consequently, an energy-efficient and reliable scheme is required for NNs to balance the above three aspects with satisfied user experience. To this end, we propose a neuron-level voltage scaling framework called NN-APP to model the impact of supply voltages on NNs from output accuracy (A), power (P), and performance (P) perspectives. We analyze the error propagation characteristics in NNs at both inter- and intra-network layers to precisely model the impact of voltage scaling on the final output accuracy at neuron-level. Furthermore, we combine a voltage clustering method and the multi-objective optimization to identify the optimal voltage islands and apply the same voltage to neurons with similar fault tolerance capability. We perform three case studies to demonstrate the efficacy of the proposed techniques.

As more emerging applications are moving to GPUs, fine-grained synchronization has become imperative. However, their performance can be severely impaired in case of frequent synchronization failures caused by high data contention. Differently from CPUs, GPUs own thousands of hardware threads and adopt single instruction multiple threads paradigm, making it impractical to deploy the CPU contention management mechanisms directly on GPUs. In this article, we design a Software Warp Controlling Framework (SWCF), which employs producer-consumer execution model and leverages GPU hardware barriers to dynamically control the execution of warps at runtime. On the basis of SWCF, we propose a contention management strategy to decrease frequent synchronization failures while avoiding the over-reducing of parallelism. We evaluate SWCF and the proposed strategy on commodity GPUs using a set of applications with fine-grained synchronization. The results show that on V100 GPU our contention management achieves a 4.7X speedup and outperforms the conventional GPU software backoff solution by 42% on average.

As a new type of micro-electro-mechanical systems (MEMS) inertial sensor, the Quartz Vibrating Beam Accelerometer (QVBA) is widely used in intelligent sweeping robots, small aircraft, navigation systems, etc. For these applications, correcting and compensating the attitude angle with the result of acceleration plays an important role to improve the measurement accuracy. The synchronization error between the measurement of the accelerometer and gyroscope attitude angle has an adverse impact on the accuracy of the attitude angle. In this paper, a synchronous acquisition scheme of the accelerometer and gyroscope attitude angle in a strapdown inertial navigation system (SINS) is proposed. At the same time, to improve the sampling accuracy and the conversion speed of QVBA, an improved equal-precision frequency measuring method is also implemented in this paper. The hardware float point unit (FPU) is used to accelerate the calculation of the frequency measurement value. The long-term cumulative error of the frequency measurement value is less than ${10}^{-4}$ . The calculation process time from sampling to attitude angle compensation calculation is reduced by 40.8%. This work has played a very good role in improving the measurement accuracy and speed of the SINS.

Ensuring the reliability of deep neural networks (DNNs) is paramount in safety-critical applications. Although introducing supplementary fault-tolerant mechanisms can augment the reliability of DNNs, an efficiency tradeoff may be introduced. This study reveals the inherent fault tolerance of neural networks, where individual neurons exhibit varying degrees of fault tolerance, by thoroughly exploring the structural attributes of DNNs. We thereby develop a hardware/software collaborative method that guarantees the reliability of DNNs while minimizing performance degradation. We introduce the neuron vulnerability factor (NVF) to quantify the susceptibility to soft errors. We propose two efficient methods that leverage the NVF to minimize the negative effects of soft errors on neurons. First, we present a novel computational scheduling scheme. By prioritizing error-prone neurons, the expedited completion of their computations is facilitated to mitigate the risk of neural computing errors that arise from soft errors without sacrificing efficiency. Second, we propose the NVF-guided heterogeneous memory system. We employ variable-strength error-correcting codes and tailor their error-correction mechanisms to the vulnerability profile of specific neurons to ensure a highly targeted approach for error mitigation. Our experimental results demonstrate that the proposed scheme enhances the neural network accuracy by 18% on average, while significantly reducing the fault-tolerance overhead.

The diversity of applications today emphasizes memory performance on numerous aspects. Some emerging data analytic workloads such as graph processing, neural network and edge data pre-procesing desire efficient memory read operation. Unfortunately, due to the necessity of dynamic refresh, modern DRAM system has to stall access during refresh cycles. As DRAM device density continues to grow, refresh operations can be a crucial throughput bottleneck. To fully unleash memory access performance, we revisit conventional refresh mechanism and DRAM architecture. We propose DR, a specific refresh mechanism that enable read and refresh operations to be done simultaneously. We devise DR DRAM, a specific memory system that can efficiently deploy DR refresh. Unlike traditional refresh, DR explores device refresh that only refreshes a designated device at a time. Meanwhile, DR increases read efficiency by recovering the inaccessible data that resides on a device under refreshing. We also propose Hybrid Refresh Main Memory (HRMM) which can designate refresh schemes (DR or traditional refresh) in a specific memory space. In this paper we detail DR's architecture and protocol design. We expect that our design can benefit many real-life tasks such as SPEC CPU2006, CNN, LLT and PageRank.