Single-phase pulsewidth modulation rectifiers suffer from ripple power pulsating at twice the line frequency. The ripple power is usually filtered by a bulky capacitor bank or an LC branch, resulting in lower power density. The alternative way is active power decoupling, which uses an active circuit to direct the pulsating power into another energy-storage component. The main dc-link filter capacitor can, therefore, be reduced substantially. This paper proposed a new scheme of active power decoupling. The circuit consists of a third leg, an energy-storage capacitor and a smoothing inductor. The topology combined the advantages of high energy-storage efficiency and low requirement on control bandwidth. Both the pulsating power from the ac source and the reactive power of the smoothing inductors are taken into consideration when deriving the power decoupling scheme. The active power filter's (APF) capacitor voltage control system consists of inner loop pole-placement control and outer loop proportional-resonant control. To enhance the steady-state performance, the capacitor voltage reference is modified in a closed-loop manner. Simulation and experimental results show that the proposed APF scheme has good power decoupling performance and is more suited for high-power applications where switching frequency is limited.

In this paper, a selective harmonic current mitigation pulsewidth modulation (SHCM-PWM) technique with low switching frequencies is proposed for grid-connected cascaded H-bridge multilevel rectifiers to fully meet harmonic requirements within extended harmonic spectrum. In the proposed technique, instead of using the voltage references to calculate switching angles for the rectifier as in conventional selective harmonic elimination-PWM (SHE-PWM) or selective harmonic mitigation-PWM (SHM-PWM), current references are used to compensate the current harmonics due to both grid voltage harmonics and rectifier input voltage harmonics so as to meet the current harmonic requirements and total demand distortion within the whole harmonic spectrum. Furthermore, the techniques to design the critical parameters including switching frequency, the highest harmonic order that can be mitigated using the proposed current-reference-based technique, and the coupling inductance that can attenuate the current harmonic orders above the highest order are investigated. With the same switching frequency, the proposed SHCM-PWM technique uses smaller coupling inductance to meet higher orders of current harmonic requirements than the conventional SHE-PWM technique. Finally, simulations and experiments were conducted to validate the proposed technique.

Soft magnetic composites (SMCs) based magnetic cores are attractive for high frequency and high power inductor design. The permeability of SMC core can be achieved by adjusting the powder size, addition of insulation material, and forming pressure to reduce the air gap loss and ease the inductor design. The nanocrystalline alloy (Fe-Cu-Nb-Si-B) with high saturation flux density and low hysteresis loss, showing potential suitability for SMC based magnetic cores. To date, nanocrystalline alloys are mostly used in form of laminated ribbons for magnetic cores but seldom used in SMC cores. Neither experimental validation of nanocrystalline powder SMC cores nor comparison with other commonly used SMC cores has been reported. In this paper, the structure and manufacturing process of nanocrystalline powder cores are introduced. The calculation of core loss is defined for the nanocrystalline powder core. The characteristics and performance of the nanocrystalline powder toroidal core are compared with those of other SMC cores such as Fe-Si powder (X flux), Fe-Ni powder (High flux), Fe-Si-Al powder (Kool Mμ), Fe-Ni-Mo powder (MPP). Experimental results at frequencies from 100 kHz to 600 kHz are provided to validate the loss calculation and feasibility of this new nanocrystalline powder core.

Miniature power semiconductor devices mounted on printed circuit boards (PCBs) are normally cooled by means of PCB vias, copper pads, and/or heatsinks. Various reference PCB thermal designs have been provided by semiconductor manufacturers and researchers. However, the recommendations are not optimal, and there are some discrepancies among them, which may confuse electrical engineers. This paper aims to develop analytical thermal resistance models for PCB vias and pads, and further to obtain the optimal design for thermal resistance minimization. First, the PCB via array is thermally modeled in terms of multiple design parameters. A systematic parametric analysis leads to an optimal trajectory for the via diameter at different PCB specifications. Then, an axisymmetric thermal resistance model is developed for PCB thermal pads where the heat conduction, convection, and radiation all exist; due to the interdependence between the conductive/radiative heat transfer coefficients and the board temperatures, an algorithm is proposed to fast obtain the board-ambient thermal resistance and to predict the semiconductor junction temperature. Finally, the proposed thermal models and design optimization algorithms are verified by computational fluid dynamics simulations and experimental measurements.

Gallium Nitride enhancement-mode high electron mobility transistors (GaN E-HEMTs) can achieve high frequency and high efficiency due to its excellent switching performance compared with conventional Si transistors. Nevertheless, GaN HEMTs exhibit a more pronounced dynamic on-state resistance RDS(on) than silicon transistors. The variation of RDS(on) is caused by both the static RDS(on) due to junction temperature rise and the dynamic RDS(on) due to the electron trapping. Without a careful decoupling analysis, it is difficult to calculate and model the dynamic RDS(on) portion. This paper introduces a comprehensive approach of dynamic RDS(on) evaluation, comprising four techniques: 1) a clamping circuit for both the hard-switching (HS) device and synchronous rectification (SR) device; 2) a junction temperature monitoring technique; 3) control of both the pulse test and soak time; 4) continuous operation of device under test. Based on the dynamic RDS(on) test results, a new model of the RDS(on) variation is developed where two coefficients: kTj and kdR are defined to model the contribution of the heating effect and the impact of the trapping effect, respectively. The RDS(on) model is validated by the comparison between the calculated and measured junction temperatures of a 650 V/30 A GaN-based half-bridge. Furthermore, a detailed loss breakdown analysis is conducted for the GaN-based hard-switching half-bridge. Results show that the switching losses, Eon and Eoff are the dominant loss factors with high switching frequency. At last, the possible efficiency improvements are also discussed in detail.

Applying the selective harmonic elimination (SHE) technique to grid-connected-cascaded modular multilevel inverters has been widely discussed in the literature. However, due to the difficulties of solving high-order nonlinear transcendental equations, the SHE technique cannot be implemented in real time so its applications are limited. This paper presents a technique to convert the nonlinear equations to a specific control system and use a look-up table, integral controllers and a decoupling controller to help the system converge to a zero-error steady state. An inner instantaneous observer is introduced to directly extract the harmonic spectrum of the output voltages without applying FFT algorithm to output step voltage waveforms. It can not only simplify software design but also eliminate the phase delay generated by conventional spectrum extracting algorithm. The proposed technique can achieve an accurate switching angle control and a fast response. Simulation and experimental results verified that the system can achieve zero-error steady state within one line period.