Frequency-dependent I/Q imbalance and frequency-independent I/Q imbalance are the major impairments in wideband zero-IF receivers, and they both cannot be ignored. In this paper, a blind calibration model is designed for compensating these I/Q imbalances. In order to accurately estimate the imbalance parameters with low cost, a classification rule is proposed according to the frequency-domain statistical characteristics of the received signal. The calibration points in the frequency-domain are divided into two groups. Then, the amplitude imbalance and the frequency-dependent phase imbalance are derived from the group of signal points and, separately, the frequency-independent phase imbalance is calculated from the group of noise points. In the derivation of the frequency-dependent phase imbalance, a general fitting model suitable for all signal points is proposed, which does not require special calculations for either DC point or f_s/2 point. Then, a finite impulse response (FIR) real-valued filter is designed to correct the impairments of received signal. The performances of the proposed calibration model are evaluated through both simulations and experiments. The simulation results show the image rejection ratio (IRR) improvement to around 35–45 dBc at high signal-to-noise ratio (SNR). Based on the mismatched data of the ADRV9009 evaluation board, the experimental results exhibit the IRR improvement of both multi-tone and wideband signals to about 30 dBc.

A generic transmitter (TX) I/Q imbalance self-calibration method, which was designed based on a hybrid analog and digital structure, is proposed in this paper. The whole calibration scheme was implemented using low-complexity digital–analog circuits based on a zero-force feedback loop. In order to eliminate the negative effect of local oscillator (LO) harmonics on the calibration, we used a variable-delay line (VDL) in the analog domain instead of the digital phase compensator. The prototype chip was fabricated within a 0.2∼5.0 GHz direct-conversion transmitter in a 65 nm CMOS process, and measurements found an image rejection ratio (IRR) of 65 dBc.

This letter proposes a parasitic elimination bootstrapped switch and a fast settling residual amplifier to be used in multiplying digital-to-analog converter (MDAC) in order to improve the performance of pipelined ADC at high frequency. The parasitic elimination bootstrapped switch improves the sampling spurious free dynamic range (SFDR) by more than 6dB by shielding the nonlinear parasitic capacitance of the MOS transistor substrate. In addition, at high frequency, the negative zero point introduced by the later stage switch-capacitor circuit (which is easy to be ignored) will seriously deteriorates the settling time of residual amplifier in the former stage. A new zero-pole elimination technique is proposed, which greatly reduces the settling time of residual amplifier by nearly 11% and further improve the performance of MDAC. Simulated in 28nm CMOS technology, as the input signal is 1.38GHz, the former stage of the pipelined ADC implements high-speed high-resolution to obtain a SFDR of 75.77dB and a signal-to-noise-plus-distortion ratio (SNDR) of 68.05dB at a sampling frequency of 2.2GS/s.