In this paper, we explore the impact of changing the growth conditions on the substrate surface during the metal-organic vapor phase epitaxy of 2D-transition metal dichalcogenides. We particularly study the growth of molybdenum disulfide (MoS ₂ ) on sapphire substrates at different temperatures. We show that a high temperature leads to a perfect epitaxial alignment of the MoS ₂ layer with respect to the sapphire substrate underneath, whereas a low temperature growth induces a 30° epitaxial alignment. This behavior is found to be related to the different sapphire top surface re-arrangement under H ₂ S environment at different growth temperatures. Structural analyses conducted on the different samples confirm an improved layer quality at high temperatures. MoS ₂ channel-based metal–oxide–semiconductor field-effect transistors are fabricated showing improved device performance with channel layers grown at high temperature.

Frequency-dependent I/Q imbalance and frequency-independent I/Q imbalance are the major impairments in wideband zero-IF receivers, and they both cannot be ignored. In this paper, a blind calibration model is designed for compensating these I/Q imbalances. In order to accurately estimate the imbalance parameters with low cost, a classification rule is proposed according to the frequency-domain statistical characteristics of the received signal. The calibration points in the frequency-domain are divided into two groups. Then, the amplitude imbalance and the frequency-dependent phase imbalance are derived from the group of signal points and, separately, the frequency-independent phase imbalance is calculated from the group of noise points. In the derivation of the frequency-dependent phase imbalance, a general fitting model suitable for all signal points is proposed, which does not require special calculations for either DC point or f_s/2 point. Then, a finite impulse response (FIR) real-valued filter is designed to correct the impairments of received signal. The performances of the proposed calibration model are evaluated through both simulations and experiments. The simulation results show the image rejection ratio (IRR) improvement to around 35–45 dBc at high signal-to-noise ratio (SNR). Based on the mismatched data of the ADRV9009 evaluation board, the experimental results exhibit the IRR improvement of both multi-tone and wideband signals to about 30 dBc.

The InAlN/GaN HEMT has been identified as a promising alternative to conventional AlGaN/GaN HEMT due to its enhanced polarization effect contributing to higher 2DEG in the GaN channel. However, the InAlN barrier usually suffers from high leakage and therefore low breakdown voltage. In this paper, we propose an asymmetrical GaN HEMT structure which is composed of an InAlN barrier at the source side and an AlGaN barrier at the drain side. This novel device combines the advantages of high 2DEG density at the source side and low electrical-field crowding at the drain side. According to the TCAD simulation, the proposed asymmetric device exhibits better drain current and transconductance compared to AlGaN/GaN HEMT, and enhanced breakdown voltage compared to InAlN/GaN HEMT. The current collapse effects have also been evaluated from the process-related point of view. Possible higher interface traps related to the two-step epitaxial growth for the asymmetric structure fabrication will not exacerbate the current collapse and reliability.

In this Letter, the impacts of the GaN cap on the gate leakage mechanisms have been investigated in the recessed-gate AlGaN/GaN high-electron-mobility transistors. The recessed gate with GaN cap removal under the gate can be a way to shrink the gate-to-channel distance, therefore improving the current density and the transconductance without sacrificing the interface properties, which play an important role in current collapse. The investigation of gate leakage current, as a reliability issue, on the recessed gate with GaN cap removal is, therefore, important. From the Igs–Vgs measurements at different temperature and stress conditions, it is found that the leakage mechanisms of the recessed-gate devices with cap removal are identical to those of the standard devices. However, the trap energy level is higher when extracted from the two-step trap-assisted tunneling mechanism at high reverse gate bias, resulting in higher leakage current for the recessed-gate device. Besides, stress measurements on the device reveal that the leakage mechanism at low reverse gate bias changes from temperature-independent before stress to temperature-dependent after stress. It is also found that a recoverable trap with a new energy level is generated after stress based on temperature-sensitive characteristics, which corresponds to the Poole–Frenkel emission mechanism.

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm² (1.2 mm² including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of −60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.