The degradation induced by ultra-high total ionizing dose in 65 nm MOS transistors is strongly gate-length dependent. The current drive decreases during irradiation, and the threshold voltage often shifts significantly during irradiation and/or high-temperature annealing, depending on transistor polarity, applied field, and irradiation/annealing temperature. Ionization in the spacer oxide and overlying silicon nitride layers above the LDD extensions leads to charge buildup as well as the ionization and/or release of hydrogen. Charge trapped in the spacer oxide or at its interface modifies the parasitic series resistance, reducing the drive current. The released hydrogen transports as H+ with an activation energy of ~ 0.92 eV. If the direction of the electric field is suitable, the H+ can reach the gate oxide interface and de-passivate Si-H bonds, leading to threshold voltage shifts. Newly created interface traps are most prominent near the source or drain. The resulting transistor responses and defect-energy distributions often vary strongly in space and energy as a result, as demonstrated through current-voltage, chargepumping, and low-frequency noise measurements.

Total-ionizing-dose (TID) mechanisms are investigated in 28-nm MOSFETs via DC-static and low-frequency-noise measurements. nMOSFETs and pMOSFETs are irradiated up to 1 Grad(SiO2) and annealed at high temperatures. TID sensitivity depends on channel-length, channel-width, and bias condition. Halo implantations improve the radiation tolerance of shorterchannel transistors. Worst-case bias for TID-induced degradation is found with high electric field applied to the gate during irradiation due to increased charge trapping in the upper corner of the STI and in the gate oxide. DC and low-frequency noise measurements show that, at doses up to 100 Mrad(SiO2), radiation-induced degradation is due primarily to positive charge buildup in the STI oxides. At ultra-high doses approaching 1 Grad(SiO2), TID degradation is influenced by charge buildup in the gate oxide and traps at or near the gate/dielectric interface and/or along the STI sidewalls. Worst-case degradation is found in narrower and longer channel devices, due to enhanced charge buildup in the shallow trench isolation (STI) oxide and along its interfaces.

Simplicity is one of the key feature for the spread of any successful technological product. Here, a method for rapid and low-cost fabrication of electrochemical biosensors is presented. This "plug, print & play" method involves inkjet-printing even in an office-like environment, without the need of highly specialized expertise or equipment, guaranteeing an ultra-fast idea to (scaled) prototype production time. The printed biosensors can be connected to a smartphone through its audio input for their impedance readout, demonstrating the validity of the system for point-of-care biosensing. Proper electrodes layout guarantees high sensitivity and is validated by finite element simulations. The introduction of a passivation method (wax printing) allowed to complete the devices fabrication process, increasing their sensitivity. Indeed, the wax allowed reducing the interference related to the parasitic currents flowing through the permeable coating of the employed substrates, which was used for the chemical sintering, thus avoiding the common thermal treatment after printing. As a case study, we used the devices to develop an electrochemical aptamer-based sensor for the rapid detection of neutrophil gelatinase-associated lipocalin (NGAL) in urine - a clinically important marker of acute kidney injury. The aptasensor platform is capable of detecting clinically relevant concentrations of NGAL with a simple and rapid smartphone readout. The developed technology may be extended in the future to continuous monitoring, taking advantage of its flexibility to integrate it in tubes, or to other diagnostic applications where cost/efficiency and rapidity of the research, development and implementation of point of care devices is a must.

This article investigates the total ionizing dose (TID) degradation mechanisms of 16-nm bulk Si FinFETs at ultrahigh doses. n- and p-FinFETs with several channel lengths are irradiated up to 1 Grad(SiO ₂ ) and then annealed for 24 h at 100 °C. Irradiated devices show significant degradation in transconductance and OFF-state leakage currents with slight subthreshold stretch-out and negligible threshold voltage shifts. At doses up to 10 Mrad(SiO ₂ ), the TID response is dominated by positive trapped charges in the shallow trench isolation (STI). At ultrahigh doses approaching 1 Grad(SiO ₂ ), dc static measurements suggest generation of trapped charge at the STI/Si interface and/or at the corner between the STI and the gate dielectric. The TID sensitivity depends on the bias condition and channel length. Halo implantations fortuitously increase the radiation tolerance of short-channel FinFETs due to the increased channel doping caused by the overlap of the source and the drain halos. The worst degradation is found when a high electric field is applied to the gate during irradiation.

In this work, the Total Ionizing Dose (TID) response of a commercial 28 nm high-k CMOS technology at ultra-high doses is measured and discussed. The degradation of pMOSFETs depends not only on the channel width, but also on the channel length. Short channel pMOSFETs exhibit a higher TID tolerance compared to long ones. We attributed this effect to the presence of the halo implantations. For short channel lengths, the drain halo can overlap the source one, increasing the average bulk doping along the channel. The higher bulk doping attenuates the radiation-induced degradation, improving the TID tolerance of short-channel transistors. The results are finally compared and discussed through Technology Computer-Aided Design simulations.

In this work, a commercial 65 nm CMOS technology is irradiated at ultra-high ionizing doses and then annealed at high temperature under different bias conditions. Experimental results demonstrate the high sensitivity of pMOSFETs to radiation-induced short-channel effects, related to the buildup of defects in spacer dielectrics. We find that the charge buildup in the spacers is insensitive to applied source-to-drain electric field, but the generation and/or annealing of interface traps strongly depends on applied drain bias and channel length. Static DC and charge pumping measurements indicate a high density of interface traps in the lateral source/drain extension regions. The worst-case bias condition corresponds to the application of a large drain-source voltage, due to the lateral electric field driving hydrogen from the spacers towards the source extension and the channel. The consequent differences in growth and annealing rates of interface traps leads to a large asymmetric degradation of the short-channel transistors. Technology computer-aided design simulations are used to qualitatively confirm the proposed degradation model.