We conducted experiments on SnO₂ thin layers to determine the dependencies between the stoichiometry, electrochemical properties, and structure. This study focused on features such as the film structure, working temperature, layer chemistry, and atmosphere composition, which play a crucial role in the oxygen sensor operation. We tested two kinds of resistive SnO₂ layers, which had different grain dimensions, thicknesses, and morphologies. Gas-sensing layers fabricated by two methods, a rheotaxial growth and thermal oxidation (RGTO) process and DC reactive magnetron sputtering, were examined in this work. The crystalline structure of SnO₂ films synthesized by both methods was characterized using XRD, and the crystallite size was determined from XRD and AFM measurements. Chemical characterization was carried out using X-ray photoelectron (XPS) and Auger electron (AES) spectroscopy for the surface and the near-surface film region (in-depth profiles). We investigated the layer resistance for different oxygen concentrations within a range of 1–4%, in a nitrogen atmosphere. Additionally, resistance measurements within a temperature range of 423–623 K were analyzed. We assumed a flat grain geometry in theoretical modeling for comparing the results of measurements with the calculated results.

Low-density parity-check (LDPC) codes are known to be one of the best error-correction coding (ECC) schemes in terms of correction performance. They have been utilized in many advanced data communication standards for which the codecs are typically implemented in custom integrated circuits (ICs). In this paper, we present a research work that shows that the LDPC coding scheme can also be applied in a system characterized by highly limited computational resources. We present a microcontroller-based application of an efficient LDPC encoding algorithm with efficient usage of memory resources for the code-parity-check matrix and the storage of the results of auxiliary computations. The developed implementation is intended for an IoT-type system, in which a low-complexity network node device encodes messages transmitted to a gateway. We present how the classic Richardson–Urbanke algorithm can be decomposed for the QC-LDPC subclass into cyclic shifts and GF(2) additions, directly corresponding to the CPU instructions. The experimental results show a significant gain in terms of memory usage and decoding timing of the proposed method in comparison with encoding with the direct parity check matrix representation. We also provide experimental comparisons with other known block codes (RS and BCH) showing that the memory requirements are not greater than for standard block codes, while the encoding time is reduced, which enables the energy consumption reduction. At the same time, the error-correction performance gain of LDPC codes is greater than for the mentioned standard block codes.