Field Programmable Gate Array (FPGA) is widely used in real-time network processing such as Software-Defined Networking (SDN) switch due to high performance and programmability. Bit-Vector (BV)-based approaches can implement high-performance multi-field packet classification, on FPGA, which is the core function of the SDN switch. However, the SDN switch requires not only high performance but also low update latency to avoid controller failure. Unfortunately, the update latency of BV-based approaches is inversely proportional to the number of rules, which means can hardly support the SDN switch effectively. It is reasonable to split the ruleset into sub-rulesets that can be performed in parallel, thereby reducing update latency. We thus present SplitBV for the efficient update by using several distinguishable exact-bits to split the ruleset. SplitBV consists of a constrained recursive algorithm for selecting the bit positions that can minimize the latency and a hybrid lookup pipeline. It can achieve a significant reduction in update latency with negligible memory growth and comparable high performance. We implement SplitBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Packet classification is widely used in Software-Defined Networking (SDN). At present, packet classification is mainly implemented by software, such as OpenvSwitch, which has the disadvantage of low performance. On the Field Programmable Gate Array (FPGA) platform, FPGA has the advantages of reconfigurability and high processing performance. The current work proposes the FPGA-based Bit-Vector algorithms in packet classification, which has the advantages of determining latency and high throughput. In the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively useless wildcards because there are plenty of wildcards in the rules. A bit-vector-based memory compression scheme named Memory-shared Bit-Vector (MsBV) is proposed. MsBV adopts a memory-shared homogeneous two-dimensional pipeline architecture, and it can reduce memory consumption and ensure the correctness of packet classification. In MsBV, we reduce memory consumption better by rearranging the bit matrix. The experimental results show that MsBV saves about 43.69% memory resources, 57.53% the number of ALUTs, and 37.59% the number of Registers compared to StrideBV of 100K OpenFlow rules.