High-performance packet classification algorithms have been widely studied during the past decade. Bit-Vector-based algorithms proposed for FPGA can achieve very high throughput by decomposing rules delicately. However, the relatively large memory resources consumption severely hinders applications of the algorithms extensively. It is noteworthy that, in the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively plenty of useless wildcards in the rules. We thus present a memory-optimized packet classification scheme named WeeBV to eliminate the memory occupied by the wildcards. WeeBV consists of a heterogeneous two-dimensional lookup pipeline and an optimized heuristic algorithm for searching all the wildcard positions that can be removed. It can achieve a significant reduction in memory resources without compromising the high throughput of the original Bit-Vector-based algorithms. We implement WeeBV and evaluate its performance by simulation and FPGA prototype. Experimental results show that our approach can save 37% and 41% memory consumption on average for synthetic 5-tuple rules and OpenFlow rules respectively.

Packet classification is widely used in Software-Defined Networking (SDN). At present, packet classification is mainly implemented by software, such as OpenvSwitch, which has the disadvantage of low performance. On the Field Programmable Gate Array (FPGA) platform, FPGA has the advantages of reconfigurability and high processing performance. The current work proposes the FPGA-based Bit-Vector algorithms in packet classification, which has the advantages of determining latency and high throughput. In the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively useless wildcards because there are plenty of wildcards in the rules. A bit-vector-based memory compression scheme named Memory-shared Bit-Vector (MsBV) is proposed. MsBV adopts a memory-shared homogeneous two-dimensional pipeline architecture, and it can reduce memory consumption and ensure the correctness of packet classification. In MsBV, we reduce memory consumption better by rearranging the bit matrix. The experimental results show that MsBV saves about 43.69% memory resources, 57.53% the number of ALUTs, and 37.59% the number of Registers compared to StrideBV of 100K OpenFlow rules.

In the present study, the performance of the moment method, in terms of accuracy and computational efficiency, was evaluated at both the macro- and microscopic levels. Three different types of non-equilibrium gas flows, including the force-driven Poiseuille flow, lid-driven and thermally induced cavity flows, were simulated in the slip and transition regimes. Choosing the flow fields obtained from the Boltzmann model equation as the benchmark, the accuracy and validation of Navier–Stokes–Fourier (NSF), regularized 13 (R13) and regularized 26 (R26) equations were explored at the macroscopic level. Meanwhile, we reconstructed the velocity distribution functions (VDFs) using the Hermite polynomials with different-order of molecular velocity moments, and compared them with the Boltzmann solutions at the microscopic level. Moreover, we developed a kinetic criterion to indirectly assess the errors of the reconstructed VDFs. The results have shown that the R13 and R26 moment methods can be faithfully used for non-equilibrium rarefied gas flows in the slip and transition regimes. However, as indicated from the thermally induced case, all of the reconstructed VDFs are still very close to the equilibrium state, and none of them can reproduce the accurate VDF profile when the Knudsen number is above 0.5.

Wide Single instruction multiple data (SIMD) architectures are very important in the compute intensive applications. The SIMD execution model is in efficient when it suffers from the divergent control flow. The divergent execution paths across loop iterations take place sequentially on SIMD, which defeats part of the efficiency advantage of SIMD execution. This paper proposesa mechanism to compact the divergent branch threads to mitigate the impact of branch thread divergence on SIMD architectures. It relaxes the SIMD execution model by allowing the distinct instruction flows to be scheduled independently, instead of one single instruction flow. It increases flexibility and mitigates the synchronization cost of co-issuing instructions from different divergent branch threads by giving the Vector processing elements (VPEs) the ability to direct their own control flow. The proposed divergent branch threads compaction mechanism improves performance by 2.56x over traditional SIMD architecture for a wide variety of general purpose parallel applications while the area overhead only increases 6.48%.