This work investigates the degradation mechanism of 1.2 kV silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET) under positive or negative long-term high-temperature gate bias (HTGB) stress. After positive long-term HTGB stress, the device shows a positive shift in threshold voltage ( ${V}_{\text {th}}{)}$ and an increase in ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}{)}$ , which mainly results from the electron traps at or near the SiC/SiO2 interface. While subjected to negative HTGB stress, the drift of $V_{\text {th}}$ is time-dependent and correlated with the gate bias. For the device biased at a low gate voltage of −10 V, due to the hole traps at or near the interface, its ${V}_{\text {th}}$ exhibits negative shift all the time. But the drift of ${V}_{\text {th}}$ for the device biased at a higher voltage of −20 V is decreased first with the stress time, then is increased with the stress time, which may result from the hole traps and the additional electron traps introduced by the tunneling effect. Through the low-frequency noise technology, it is demonstrated that the trap density of the device biased at higher negative gate voltage of −20 V has been increased up to three times.

In this work, we have comprehensively investigated the degradation behaviors and mechanism of 1.2 kV silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under repetitive surge current stress. The experimental results show that the negative drift of threshold voltage ( $\textit{V}_{\text{th}}$ ) is related to the gate turn-off voltage and the surge current. The gate leakage current ( $\textit{I}_{\text{gss}}$ ) increases by about one order of magnitude after the stress. The deterioration of the electrical parameters is considered to be the gate oxide degradation associated with the increase of SiC/SiO $_{\text{2}}$ interface traps. By using the low-frequency noise (LFN) technique, it is demonstrated that the trap density of the device with the most severe degradation after the stress becomes 3.5 times the initial one. On the other hand, we observed that the voltage drop ( $\textit{V}_{\text{sd}}$ ) of the body diode and on-resistance ( $\textit{R}_{\text{ds(\biosc{on})}}$ ) increased. It is attributed to the cumulative degradation process of package with the appearance of fatigue in the bond wire induced by the thermo-mechanical stress during the surge test. This work can serve as a valuable reference for the reliability of SiC MOSFETs.

In this work, we have comprehensively studied the forward/reverse G-to-S electrostatic discharge (ESD) robustness for Ohmic-gate p-GaN HEMT. It is found that Ohmic-gate p-GaN HEMT exhibits superior G-to-S ESD robustness than Schottky-gate p-GaN HEMT with similar current capacity. First, Ohmic-gate p-GaN HEMT possesses a high forward/reverse second breakdown current ( ${I}_{\text {SF}}/I_{\text {SR}}$ ) of 9.3/2.7 A, while the value is 2.0/0.1 A for Schottky-gate p-GaN HEMT. Correspondingly, the equivalent forward/reverse human body model (HBM) failure voltages ( ${V}_{\text {HBM-F}}/{V}_{\text {HBM-R}} = {1500} \Omega \times {I}_{\text {SF}}/{I}_{\text {SR}}$ ) are 14/4.05 kV and 3/0.15 kV for Ohmic-gate and Schottky-gate p-GaN HEMTs, respectively. In addition, Schottky-gate p-GaN HEMT exhibits obvious changes in its ON-state current ( $\Delta {I}_{ \mathrm{\scriptscriptstyle ON}}$ = 0.8/0.7 A), threshold voltage ( $\Delta {V}_{\text {TH}}$ = 0.23/0.35 V), G-to-S leakage after the forward/reverse repetitive G-to-S ESD stress. While there is no obvious change ( $\Delta {I}_{ \mathrm{ON}}$ = 0 A and $\Delta {V}_{\text {TH}}$ = 0 V) in Ohmic-gate p-GaN HEMT, which may be attributed to that there are numerous holes to recombine the electrons trapped at the recombination center. But for Schottky-gate p-GaN HEMT, there is no enough holes to recombine the electrons trapped at the recombination center, due to the Schottky barrier at gate region.

In this paper, input capacitance ( C _ISS ) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. C _ISS includes gate-to-source capacitance ( C _GS ) and gate-to-drain capacitance ( C _GD ). In comparison with the normally-on HEMTs, it is found that the phenomenon of C _ISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of C _ISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of C _GS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing C _GS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of C _GD . Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on C _ISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the C _ISS related capacitance design and gate driver optimization of the devices.

In this article, an analytical model on the influence of the acceptor-type trap on the 2-dimensional electron gas (2DEG) density is proposed for GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Based on the charge-control method, a numerical analysis of the 2DEG in both the subthreshold and above-threshold regions is carried out with the deep-level and band-tail acceptor-type traps at the AlGaN/insulator interface and the AlGaN/GaN interface. In particular, the influence of the acceptor-type trap on the 2DEG density and the gate-control capability in the subthreshold region is modeled for the first time. The results have shown that the acceptor-type trap plays an important role in weakening the gate-control capability of the 2DEG density in the subthreshold region. The experimental results, together with the modeling and numerical calculations, have shown consistent 2DEG density values under various gate voltages, which verify the proposed model.

In this work, the interaction between hydrogen poisoning (HP) and bias stress in AlGaN/GaN MIS-HEMTs, which incorporate a SiNx gate dielectric, is investigated. The transfer characteristics show that a hydrogen-poisoned device exhibits a 1.15-V-negative threshold voltage (V _th ) shift, a significant direct current (DC) ON-resistance (RON_DC) decrease, and a subthreshold swing (SS) decrease with respect to a fresh device, whereas the max-gm remains unchanged after excluding the effect of RON_DC. Moreover, the border trap energy distribution remains almost unaffected before and after HP, indicating that the border traps are insensitive to HP. The experimental results show that HP causes passivation in the interface states at the SiNx/AlGaN interface and introduces mobile H ⁺ ions in the bulk SiNx, resulting in the negative V _th shift, RON_DC decrease, and SS decrease. After applying a forward-bias stress on the gate, the H ⁺ ions in the bulk SiNx underneath the gate electrode drift toward the two-dimensional electron gas (2DEG) and annihilate with electrons, resulting in the irreversible positive V _th shift. The H ⁺ ions in the bulk SiNx beyond the gate electrode(gate-to-drain- and gate-to-source) remain unchanged, resulting in an unchanged RON_DC. This conclusion is significant for the AlGaN/GaN MIS-HEMT reliability optimization against HP, and it is particularly useful in spatial applications.