A near field scanning is usually time-consuming to map the electromagnetic field along the surface of a device. In this paper, a dual probe is proposed with a U-shaped loop to sense radio-frequency (RF) magnetic and electric fields simultaneously, so that the one-time scanning by the dual probe can replace the two-time scanning by single detector probes. Different from the traditional near field scanning by using a single detector probe and spectrum analyzer, the proposed scanning can be achieved by the two-output probe and a two-port vector network analyzer connecting to the probe. The efficient near field scanning measurements of the electric and magnetic field on a conductorbacked coplanar waveguide transmission line and an RF power divider by using the dual probe are in agreement with those by using two single detector probes.

To measure the magnetic near field with high common mode noise rejection, a probe with the differential and symmetrical structure forming a detection loop is developed. Such measurement is performed by using a two-port vector network analyzer (VNA), and validated by using a microstrip line as device under test (DUT). In comparison to the measurement with traditional single-output magnetic near field probe, the electric field suppression of the proposed measurement can be improved by at least 10 dB in the frequency range of 3∼11 GHz, while the other characteristics basically remain unchanged.

Power cycling test (PCT) is an effective method to evaluate the SiC mosfet s' long-term reliability, including lifetime and degradation mechanisms. Some of the aging precursors of PCT have been identified in the previous literature. But when multiple failure mechanisms compete with each other, the individual precursors are nullified. Although PCT is mainly used to evaluate the package reliability, there are still unresolved problems due to the gate oxide reliability of SiC mosfet , and the repeated gate stress of the power cycling has different effects on the devices with different gate structures. This article presents a comprehensive investigation of the aging precursors and failure mechanism of three typical commercial SiC mosfet s with different gate structures through PCTs under two different conduction modes. Degradation-related essential precursors and possible causes behind them are discussed. The failure mechanisms and correlation with the degradation state of different devices are studied in depth. In addition, the effects of PCT under different conduction modes on failure mechanism and lifetime have been investigated.

In this article, we experimentally investigate the degradation mechanisms of GaN high-electron mobility transistors (HEMTs) with p-type gate during long-term high-temperature reverse bias (HTRB) stress and negative bias temperature instability (NBTI) stress. Based on a number of stress/recovery experiments, we demonstrate that HTRB stress could lead to hole emission in the p-GaN layer, making threshold voltage (Vth) positively shift, while NBTI stress could result in detrapping at the AlGaN/GaN interface or the AlGaN layer and make Vth negatively shift. It is also found that the temperature rise can suppress the positive Vth shift and accelerate its recovery process in HTRB experiments.

This work investigates the degradation mechanism of 1.2 kV silicon carbide (SiC) metal oxide semiconductor field-effect transistor (MOSFET) under positive or negative long-term high-temperature gate bias (HTGB) stress. After positive long-term HTGB stress, the device shows a positive shift in threshold voltage ( ${V}_{\text {th}}{)}$ and an increase in ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}{)}$ , which mainly results from the electron traps at or near the SiC/SiO2 interface. While subjected to negative HTGB stress, the drift of $V_{\text {th}}$ is time-dependent and correlated with the gate bias. For the device biased at a low gate voltage of −10 V, due to the hole traps at or near the interface, its ${V}_{\text {th}}$ exhibits negative shift all the time. But the drift of ${V}_{\text {th}}$ for the device biased at a higher voltage of −20 V is decreased first with the stress time, then is increased with the stress time, which may result from the hole traps and the additional electron traps introduced by the tunneling effect. Through the low-frequency noise technology, it is demonstrated that the trap density of the device biased at higher negative gate voltage of −20 V has been increased up to three times.

In this work, we have comprehensively investigated the degradation behaviors and mechanism of 1.2 kV silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under repetitive surge current stress. The experimental results show that the negative drift of threshold voltage ( $\textit{V}_{\text{th}}$ ) is related to the gate turn-off voltage and the surge current. The gate leakage current ( $\textit{I}_{\text{gss}}$ ) increases by about one order of magnitude after the stress. The deterioration of the electrical parameters is considered to be the gate oxide degradation associated with the increase of SiC/SiO $_{\text{2}}$ interface traps. By using the low-frequency noise (LFN) technique, it is demonstrated that the trap density of the device with the most severe degradation after the stress becomes 3.5 times the initial one. On the other hand, we observed that the voltage drop ( $\textit{V}_{\text{sd}}$ ) of the body diode and on-resistance ( $\textit{R}_{\text{ds(\biosc{on})}}$ ) increased. It is attributed to the cumulative degradation process of package with the appearance of fatigue in the bond wire induced by the thermo-mechanical stress during the surge test. This work can serve as a valuable reference for the reliability of SiC MOSFETs.