Multi-layer graphene nanoribbons (MLGNRs) material has been a potential solution to replace conventional Cu for next-generation on-chip interconnects. Based on equivalent single conductor model, this paper extracts the equivalent resistance-inductance-capacitance parameters for MLGNRs with consideration of edge roughness and Fermi level. A distributed circuit model for a pair of coupled MLGNR interconnects is provided, with both capacitive and inductive coupling taken into account, and validated against the Spice results and the predicted experiment results in frequency and time domains. Using the proposed model, the impact of various dimensional and technology parameters on the transfer gain and crosstalk delay is investigated for the global MLGNR interconnects at different phase modes. It is demonstrated that MLGNR interconnects with smooth edge exhibit higher transfer gain and lower crosstalk delay in comparison to its Cu counterpart at same dimension. However, edge roughness in the present fabrication technologies is inevitable that significantly deteriorates the propagation performance and the performance difference due to edge roughness is relatively less in wider MLGNR interconnects. Moreover, it is shown that side contact MLGNR interconnects have better electrical performance than that of top contact MLGNR interconnects at short interconnect length in comparison to that at long interconnects due to the domination of in-layer resistance. The results presented in this paper would be helpful to fully understand the propagation characteristics and provide guidelines for signal integrity analysis of MLGNR interconnects.

Chiplet technology has become a hotspot in the post-Moore era and widely used in portable electronic products. However, the compact and complex internal structure of Chiplet packaging may seriously degrade the drop reliability. In this work, the drop reliability of Chiplet is analyzed, modeled, simulated, quantitatively predicted and optimized. A variety of Chiplet quarter models is established, and the distribution of deformation and stress is analyzed using the finite element method, revealing that the Si interposer is a critical location. Predictions are made for more complex multi-layer stacking structures, and fitting curves are obtained to achieve rapid drop reliability prediction. The impact of Si interposer thickness on the reliability of critical location during impact is investigated, showing that a thicker Si interposer can improve reliability. Based on these findings, a structural design method is proposed to significantly enhance Chiplet reliability, reducing deformation at critical location by 98.4% and maximum stress on the Si interposer by 39.9%.

Based on the extracted resistance, inductance, capacitance, and conductance parameters, this paper introduces the distributed transmission line model of silicon-core coaxial through-silicon vias (CTSVs), in which the vertical interconnect is made of a Cu-coated silicon pole. The proposed model is validated against a commercial electromagnetic simulation tool, showing it is highly accurate up to 100 GHz. Using the proposed model, the impact of various material properties and physical parameters on the electrical performance of the silicon-core CTSVs is investigated. It is observed that the thickness of the plated Cu and isolation dielectric are two important parameters that determine the electrical performance of silicon-core CTSVs. Performance comparison shows that the proposed silicon-core CTSVs provide a comparable performance to standard Cu-based CTSVs and better performance to the conventional signal-ground TSV pairs. The results in this paper would provide some design guides for silicon-core CTSVs in 3-D integration.

Due to low dielectric loss and low cost, glass is developed as a promising material for advanced interposers in 2.5D and 3D integration. In this study, through glass vias (TGVs) are used to implement inductors for minimal footprint and large quality factor. Based on the proposed physical structure, the impact of various process and design parameters on the electrical characteristics of TGV inductors is investigated with 3D electromagnetic simulator HFSS. It is observed that TGV inductors have identical inductance and larger quality factor in comparison with their through silicon via (TSV) counterparts. Using TGV inductors and parallel plate capacitors, a compact 3-D band-pass filter (BPF) is designed and analyzed. Compared with some reported BPFs, the proposed TGV-based circuit has an ultra-compact size and excellent filtering performance.

This paper presents a novel approach called simultaneous wireless strain sensing and energy harvesting (SWSSEH) from multiple piezo-patches, which is intended for self-powered structural health monitoring (SHM) applications. The EH subsystem is mainly the self-powered extended synchronous electric charge extraction (eSECE) interface based on double cross-coupled rectifying structure and a single flyback transformer, which is able to harvest energy from multiple piezo-patches. And, the WSS subsystem is mainly the low-power multiplexing analog front end (MAFE), which is designed to process the multichannel strain signals. The innovation of the proposed approach is that energy harvesting and strain sensing can actually work simultaneously without interfering with each other. The prototype is implemented based on discrete components and tested with an emulated SHM system. Experimental results show the EH subsystem can produce 5.45 mJ energy in 100 s under 108 μE and 30.4 Hz dynamic strain. The average current consumption of the WSS subsystem is 7.53 μA, and the required energy in a 100 s is 2.49 mJ, which means the system is able to self-start even if the battery is exhausted. Additionally, the self-powered capacity can be further improved in a practical SHM system since more piezo-patches can be employed.

Piezoelectric energy harvesting (PEH) is a promising solution to provide life-time energy for ultra-low power electronics such as wireless sensor nodes. Synchronous electric charge extraction (SECE) technique can optimize the extracted power from a PEH device regardless of the connected load; however, its performance degrades seriously when the PEH device is in strongly-coupled. In this paper, a new technique called synchronous electric charge partial extraction (SECPE) is proposed, which is able to address the mentioned problem. It extracts an appropriate portion of piezoelectric energy in a single-time operation by employing the optimal LC oscillation time. The analytical relation between the normalized extracted power and LC oscillation time is derived. Theoretical predictions confirmed by the simulated results show that the optimal duration time is not fixed for different PEH devices. It should be larger than, approximately or smaller than 0.25TLC when the PEH device is weakly-coupled, moderately-coupled or stronglycoupled, respectively. The proposed SECPE technique takes a great advantage especially for these PEH devices being weaklycoupled or strongly-coupled and its performance improves by at least 30% compared with the original SECE technique. Meanwhile, its performance does not degrade even the PEH device is in strongly-coupled.