Sub-mm circuit design requires accurate on-wafer characterization of passive and active devices. In industry, characterization of these devices is often performed with off-wafer SOLT calibration. In this work, validity of this characterization procedure above 110 GHz is investigated by an exhaustive study of on-wafer and alumina off-wafer calibration using measurement and electromagnetic (EM) simulation up to 500 GHz. The EM simulation is performed at two different levels, first at the intrinsic level of the devices under test for reference and afterward up to the probe level to simulate different standards used in the off-wafer calibration or in the on-wafer calibration in presence of the probe. Further, EM simulation data is calibrated with the same procedures and tools that is used in the measurement; therefore, it includes the probe-to-substrate coupling. In addition, precise EM model of a commercial impedance standard substrate (ISS) is developed and used to perform the SOLT calibration. A good agreement is observed between measurement and EM modelling for the off-wafer calibration as well as for the on-wafer calibration. Results clearly highlights a limitation of alumina off-wafer methodology above 200 GHz for characterization of Silicon based technologies. Finally a discussion is given on the pros and cons of the off-wafer and on-wafer methodologies.

This paper presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results (- characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented.

This paper investigates on-wafer characterization of SiGe HBTs up to 500 GHz. Test structures for on-wafer thru-reflect-line (TRL) calibration have been designed and are presented. The TRL calibration method with silicon standards has first been benchmarked through electromagnetic simulation. Passive and active components are then characterized up to 500 GHz. The slight discontinuities between the frequency bands are explored. A specific focus was placed on incorrect horizontal probe positioning as well as on probe deformation, resulting in a better assessment of possible measurement errors.

In this paper, we present on-silicon structures on-wafer measurements up to 500 GHz and a comprehensive electromagnetic (EM) simulation analysis to understand non-ideal behaviour in the measured data. The EM simulations are performed in such a way that the simulation setup remains very close to the physical measurement environment where a faithful true EM model of the RF probes is an essential requirement. In this process, four different RF probes used during measurements in the frequency bands 1 GHz - 110 GHz, 140 GHz - 220 GHz, 220 GHz - 325 GHz and 325 GHz - 500 GHz are designed in the EM simulator. We also highlight the importance of the frequency band-specific probe models to develop a deep understanding of the problems encountered in the sub-THz and THz measurements.

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature.