This paper examines aspects of design technology required to explore advanced logic-circuit design using carbon nanotube field-effect transistor (CNTFET) devices. An overview of current types of CNTFETs is given and highlights the salient characteristics of each. Compact modeling issues are addressed and new models are proposed implementing: 1) a physics-based calculation of energy conduction sub-band minima to allow a realistic analysis of the impact of CNT helicity and radius on the dc characteristics; 2) descriptions of ambipolar behavior in Schottky-barrier CNTFETs and ambivalence in double-gate CNTFETs (DG-CNTFETs). Using the available models, the influence of the parameters on the device characteristics were simulated and analyzed. The exploitation of properties specific to CNTFETs to build functions inaccessible to MOSFETs is also described, particularly with respect to the use of DG-CNTFETs in fine-grain reconfigurable logic.

A new scalable electrical compact model for the Graphene FET devices is proposed. Starting from Thiele's quasianalytical model, the equations are modified to be fully compatible with SPICE-like circuit simulation. Compared to Meric et al. model, the charge model is improved. This large signal model has been implemented in Verilog-A code and can be used for simulation in a standard circuit design environment such as Cadence or ADS. This model has been verified using different measurements from the literature, and furthermore, its scalability is demonstrated.

This paper presents Si/SiGe:C and InP/GaAsSb HBTs which feature specific assets to address submillimeter-wave and THz applications. Process and modeling status and challenges are reviewed. The specific topics of thermal and substrate effects, reliability, and HF measurements are also discussed.

We present a computationally efficient physics-based compact model designed for the conventional CNTFET featuring a MOSFET-like operation. A large part of its novelty lies on the implementation of a new analytical model of the channel charge. In addition, Boltzmann Monte Carlo (MC) simulation is performed with the challenge to cross-link this simulation technique to the compact modeling formulation. The comparison of the electrical characteristics obtained from the MC simulation and from the compact modeling demonstrates the compact model accuracy within its range of validity. Then, from a study of the CNT diameter dispersion for three technological processes, the compact model allows us to determine the CNTFET threshold voltage distribution and to evaluate the resulting dispersion of the propagation delay from the simulation of a ring oscillator.

This paper presents a computationally efficient physics-based compact model for the Schottky barrier (SB) carbon nanotube field-effect transistor (CNTFET). This compact model includes a new analytical formulation of the channel charge, taking into account the influence of the source and drain SBs. Compact model simulation results (- characteristic and channel density of charge) as well as Monte Carlo simulation results, which are provided by a recent work, will be given and compared to each other and also to experimental data to validate the used approximations. Good agreement is observed over a large range of gate and drain biases. Furthermore, a scaling study is presented to examine the impact of technological parameters on the device figure of merit. Then, for the assessment of the SB on circuit performances, traditional logical circuits are designed using the SB-CNTFET compact model, and results are compared with a conventional CNTFET with zero-SB height. Finally, exploiting the particular properties of SB-CNTFETs, a three-valued static memory that is suitable for high density integration is presented.