This paper presents a comprehensive review of engineering techniques employed to enhance the quality factor (Q-factor) of silicon-based on-chip inductors across MHz-to-GHz frequency domains. The performance of CMOS on-chip inductors is often bottlenecked by the substrate losses, parasitic effects and resistive losses, which degrade the Q-factor. Numerous engineering techniques including substrate engineering, ground plane engineering, layout engineering and material engineering are analyzed and discussed. Substrate engineering such as substrate isolation and micromachining, ground plane engineering such as patterned ground shield and defected ground shield, layout engineering such as multilayer stacking and geometry modulation, material engineering such as magnetic core integration and conductor lamination are all investigated. A comparative evaluation of these techniques highlights the optimum approaches for attaining high-Q inductors in silicon process, mainly for CMOS compatibility.

In this paper, a CMOS Class-J Doherty power amplifier (PA) integrating a Class-G driver and an Impedance-Modulated-Quadrature-Transformer (IMQT) to enhance back-off efficiency for multimode operations is presented. The Class-J Doherty PA utilizes a second harmonic termination to improve its efficiency. To further augment efficiency at deep back-off output power, a single-supply-rail Class-G driver operates with the IMQT, modulating the interstage impedance between the driver and the Doherty stages. The IMQT features a stacked transformer architecture and dynamically adjusts its impedance by switching a floating, intermediate coil between the transformer's primary and secondary windings. A comparator regulates the IMQT based on the Class-G driver's operation. The IMQT-DPA, fabricated using a 65nm CMOS process, operates at a center frequency of 28 GHz with a supply headroom of 1.8V. The PA achieves an average output power of 14 dBm with a back-off efficiency of 21%, representing a 1.4-fold efficiency enhancement compared to conventional Class-B operation. Under low-power mode (V_DD/2) with a Class-G driver operation, the average output power is 11.3 dBm with a 1.3-fold efficiency improvement.

This paper presents a high speed 16-bit hybrid Digital-to-Analog converter (DAC) featuring an innovative digital filtering mechanism designed to eliminate glitches and ensure high signal integrity at an operational speed of 1 GS/s. Fabricated using a 65 nm process and operating on a 1 V supply, the hybrid DAC integrates a current-steering architecture for the six most significant bits (MSB) and a binary-weighted resistive ladder for the ten least significant bits (LSB), effectively managing power consumption. Occupying an active area of 0.06 mm ² , the DAC consumes 45 mW of power. It demonstrates differential nonlinearity (DNL) ranging from -0.27 to +0.25 LSB and integral nonlinearity (INL) from -0.33 to +0.34 LSB. Performance metrics at the Nyquist frequency include a spurious-free dynamic range (SFDR) of 72 dB and a signal-to-noise-and-distortion ratio (SNDR) of 70 dB, yielding a figure of merit (FOM) of 13.83 fJ/step. The DAC demonstrates resilience to process, voltage, and temperature (PVT) variations, with a deviation of less than 4%, confirming its reliability for the 5G New Radio (NR) sub-6 GHz application. The proposed hybrid DAC provides a fast, accurate, and power-efficient solution for high-speed, high-resolution data conversion catering to the demanding requirements of 5G NR sub-6 GHz systems.