Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.

This brief presents a CMOS power amplifier (PA) employing a digitally-assisted analog pre-distorter (DAAPD) reconfigurable linearization technique to reduce the back-off output power (PBO) for multiband operation. The proposed DAAPD optimizes the interstage load impedance between the driver and the main stage by changing the transconductance of the driver amplifier and its active load.We also utilize the DAAPD to optimize the PA when subjected to process-voltagetemperature (PVT) variations. Fabricated in 130-nm CMOS, the DAAPDPA operates from 1.7 to 2.7 GHz with a 3 dB back-off output power efficiency of 35% to 38% while fulfilling the stringent adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of a 20-MHz 16-QAM LTE signal. With a continuous wave (CW) signal, the DAAPD-PA achieves a maximum output power of 27 to 28 dBm across frequencies of interest with supply headroom of 3.3 V. Finally, the DAAPD-PA covers 20 LTE bands with reduced back-off output power.

Radio frequency energy harvesting (RFEH) is one form of renewable energy harvesting currently seeing widespread popularity because many wireless electronic devices can coordinate their communications via RFEH, especially in CMOS technology. For RFEH, the sensitivity of detecting low-power ambient RF signals is the utmost priority. The voltage boosting mechanisms at the input of the RFEH are typically applied to enhance its sensitivity. However, the bandwidth in which its sensitivity is maintained is very poor. This work implements a tunable voltage boosting (TVB) mechanism fully on-chip in a 3-stage cross-coupled differential drive rectifier (CCDD). The TVB is designed with an interleaved transformer architecture where the primary winding is implemented to the rectifier, while the secondary winding is connected to a MOSFET switch that tunes the inductance of the network. The TVB enables the sensitivity of the rectifier to be maintained at 1V DC output voltage with a minimum deviation of −2 dBm across a wide bandwidth of 3 to 6 GHz of 5G New Radio frequency (5GNR) bands. A DC output voltage of 1 V and a peak PCE of 83% at 3 GHz for −23 dBm input power are achieved. A PCE of more than 50% can be maintained at the sensitivity point of 1 V with the aid of TVB. The proposed CCDD-TVB mechanism enables the CMOS RFEH to be operated for wideband applications with optimum sensitivity, DC output voltage, and efficiency.

This paper presents a comprehensive review of engineering techniques employed to enhance the quality factor (Q-factor) of silicon-based on-chip inductors across MHz-to-GHz frequency domains. The performance of CMOS on-chip inductors is often bottlenecked by the substrate losses, parasitic effects and resistive losses, which degrade the Q-factor. Numerous engineering techniques including substrate engineering, ground plane engineering, layout engineering and material engineering are analyzed and discussed. Substrate engineering such as substrate isolation and micromachining, ground plane engineering such as patterned ground shield and defected ground shield, layout engineering such as multilayer stacking and geometry modulation, material engineering such as magnetic core integration and conductor lamination are all investigated. A comparative evaluation of these techniques highlights the optimum approaches for attaining high-Q inductors in silicon process, mainly for CMOS compatibility.

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, V_REF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm². The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from −40 °C to 125 °C, and a power supply rejection ratio of −90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature.

This brief reports a 0.92-GHz two-stage power amplifier (PA) in 130-nm CMOS process with improved back-off power efficiency and linearity. The two key techniques are: a switching mechanismfor adaptive device sizing of the power stage, and a high-Q compact inductor (HQCI). The PA is designed to operate in low power (LP) mode and high power (HP) mode by using an NMOS pass transistor as a switch. The PA measures a peak output power (Pout) of 27 dBm with a peak power added efficiency (PAE) of 44%. The maximum linear output power reaches 21.5 dBm thanks to our unique HQCI-based outputmatching network. At the back-off output power, a 10% increment in PAE is achieved by switching the size of the power stage with the MOS switch. Maximum Pout of 21.5 dBm is measured below -30 dBc ACLR and 4%EVM for the 16-QAM/20 -MHz input modulated signal. The PA has an overall chip size of 1.382 × 1.425 mm2.