This Brief reports a cross-coupled differential-drive (CCDD) rectifier with a wide dynamic range (DR) in its power conversion efficiency (PCE). Specifically, it features a self-body-biasing technique to reduce the forward V _th , along with the diode-connected MOSFETs to stem the reverse-leakage current while improving the forward current. The merits of our CCDD rectifier are exemplified via two input-capacitor-coupling configurations: shared-capacitor coupling (SCC) and individual-capacitor coupling (ICC). Fabricated in 0.13- μm CMOS, the SCC-CCDD and ICC-CCDD measure a DR of 13 and 14.5 dB, respectively, for a PCE >40%. Alternatively, the SCC-CCDD exhibits a peak PCE of 83.7% with a sensitivity of -19.2 dBm at 1 V, whereas the ICC-CCDD shows a peak PCE of 80.3% with a sensitivity of -18.7 dBm.

In this paper, the evolution and milestones of RFEH and related breakthroughs over the years are reviewed and presented. The review begins with an overview of the surging energy crisis due to the increasing demand for wireless communication devices. Furthermore, the RFEH mechanism that discusses the frequency bands utilized, the near field, and the far-field propagation are also presented. Various rectification techniques in CMOS RFEH, from the fundamental rectification method to cross-coupled-differential-drive (CCDD), are also examined and discussed. The performance is gauged through harvested output DC voltage and the power conversion efficiency (PCE) as well as the RF input power sensitivity. An assessment on the non-CMOS RFEH that includes the Schottky diode and Rectenna is also concisely described to analyze their contribution to RFEH’s performances enhancement. Finally, a particular highlight of the 5G RFEH in mmWave is provided in presenting this work as an ongoing future solution to reduce the electronic circuit’s battery dependency. The pros and cons of all the presented RFEHs are summarized and discussed as well. Continuous research and development activities are extensively being executed in developing a system that could ultimately solve the world’s energy crisis, and RFEH seems to be a revolutionary approach.

Bulky off-chip inductors are predominantly adopted for inductive-based step-up DC-DC converter in RF energy harvesting (RFEH) systems, which impose a restriction in physical form factor for miniaturized device. This article review and explores the capacitive-based step-up DC-DC converters (charge-pump) as voltage boosting element for low-voltage RFEH systems. An overview of RFEH is established and a comprehensive review of CMOS charge-pump is followed along with the complementary frequency generation circuit used as a clocking element. Key design considerations of charge-pump circuits are included here along with recommendations to circumvent its bottlenecks for future development in RFEH systems.

Recent development and technology advancement in wireless communication systems to accommodate higher data rate poses a great challenge for wideband operation. This is due to the employment of modulation scheme such as OFDM which is subject to high peak to average ratio (PAPR). Hence communication systems such as LTE has to operate in multiple operating bands at the moment in order to transmit the OFDM signals linearly with high gain. The power amplifier serves as the bottle neck for high gain linear operation over wide bandwidth. This paper addresses this issue and further presents a novel integrated feedback and analog pre-distortion linearization technique as a solution to achieve wideband flat gain and linear output power while preserving the power amplifier’s Power Added Efficiency (PAE). A maximally flat gain is achieved through the dual parallel feedback technique. The analog pre-distorter (APD) on the other hand introduces an optimum third order nonlinear signal components cancellation mechanism over wide frequency range. A prototype of 700MHz to 2.5GHz power amplifier is implemented in 0.25 μm PHEMT. It achieves an input and output return loss of less than -10dB followed by flat power gain of 20dB across the operating band while sustaining an unconditional stability performance up to 20GHz. With 1-dB compression point output power (P1dB) of 24.0dBm, the PA delivers an OIP3 of more than 40dBm with peak PAE of 66%. The fully integrated circuit consumes an area of 0.8mm2. The proposed circuit serves to be a good solution to be integrated as a part of the wideband transmitter system for picocell application.

The performance of low-powered transceivers is required to meet stringent specifications for an advanced wireless radio application. It is critical for a voltage-controlled oscillator (VCO) to meet multi-standard and multiple frequency operation with low-power consumption and amplitude enhanced complementary mode of operation. This paper proposes a novel technique for wide tuning range in a complementary class-C VCO employing a capacitive-source degeneration (CSD) to meet multi-standard operation for low-power transceivers. The technique that employs two sets of symmetrical split PMOS biased current source operating in the subthreshold region achieves the desired low phase noise (PN) performance at a tuning range of 2.2-2.9 GHz with a supply headroom of 1.2 V. The control of the dc bias point reduces the conduction angle, which improves the current efficiency, power consumption, and PN. Concurrently, an auxiliary -g _m NMOS only class-B oscillator is incorporated to mitigate the start-up issue of the class-C VCO. At the center frequency of 2.45 GHz, the proposed VCO achieves a power consumption of 1.73 mW, phase noise of -120 dBc/Hz at the 1-MHz offset, and a figure-of-merit (FoM) of 185.41 dBc/Hz at 1 MHz. The total active chip area is only 0.3-mm ² excluding bond pads. The proposed VCO serves as a promising solution for low-power wireless communication systems.

Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.