A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm² including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.

O2 plasma-based digital etching of Al0.25Ga0.75N with a 0.8 nm AlN spacer on GaN was investigated using an inductively coupled plasma etcher. Silicon oxide layer was used as the hard mask. At 40 W RF bias power and 40 sccm oxygen flow, the etch depth of Al0.25Ga0.75N was 5.7 nm per cycle. The 0.8 nm AlN spacer layer acted as an etch-stop layer in three cycles. The surface roughness improved from 0.66 to 0.33 nm after the three and seven digital etch cycles. Compared to the dry etch only approach, this technique smoothed the surface instead of causing surface roughening. Compared to the selective thermal oxidation with a wet etch approach, this method is less demanding on the epitaxial growth and saves the oxidation process. It was shown to be effective in precisely controlling the AlGaN etch depth required for recessed-AlGaN HEMTs.

Due to the piezoelectric nature of GaN, the two-dimensional electron gas (2DEG) in AlGaN/GaN high electron mobility transistor (HEMT) could be engineered by strain. In this work, SiN _x deposited using dual-frequency plasma-enhanced chemical vapor deposition (PECVD) was used as a stressor. The output performance of the devices was dominated by the surface passivation instead of the strain effect. However, the threshold voltage was increased by the liner-induced strain, supporting strain engineering as an effective approach to pursue the normally-off operation of AlGaN/GaN HEMTs.

In this paper, DC, transient, and RF performances among AlGaN/GaN HEMTs with a no field plate structure (basic), a conventional gate field plate structure (GFP), and a double floating field plate structure (2FFP) were studied by utilizing SILVACO ATLAS 2D device technology computer-aided design (TCAD). The peak electric fields under the gate in drain-side can be alleviated effectively in 2FFP devices, compared with basic and GFP devices, which promotes the breakdown voltage (BV) and suppresses the current collapse phenomenon. As a result, the ON-resistance increase caused by the current collapse phenomena is dramatically suppressed in 2FFP ~19.9% compared with GFP ~49.8% when a 1 ms duration pre-stress was applied with V_ds = 300 V in the OFF-state. Because of the discontinuous FP structure, more electric field peaks appear at the edge of the FFP stacks, which leads to a higher BV of ~454.4 V compared to the GFP ~394.3 V and the basic devices ~57.6 V. Moreover, the 2FFP structure performs lower a parasitic capacitance of C_gs = 1.03 pF and C_gd = 0.13 pF than those of the GFP structure (i.e., C_gs = 1.89 pF and C_gd = 0.18 pF). Lower parasitic capacitances lead to a much higher cut-off frequency (f_t) of 46 GHz and a maximum oscillation frequency (f_max) of 130 GHz than those of the GFP structure (i.e., f_t = 27 GHz and f_max = 93 GHz). These results illustrate the superiority of the 2FFP structure for RF GaN HEMT and open up enormous opportunities for integrated RF GaN devices.