In this paper, DC, transient, and RF performances among AlGaN/GaN HEMTs with a no field plate structure (basic), a conventional gate field plate structure (GFP), and a double floating field plate structure (2FFP) were studied by utilizing SILVACO ATLAS 2D device technology computer-aided design (TCAD). The peak electric fields under the gate in drain-side can be alleviated effectively in 2FFP devices, compared with basic and GFP devices, which promotes the breakdown voltage (BV) and suppresses the current collapse phenomenon. As a result, the ON-resistance increase caused by the current collapse phenomena is dramatically suppressed in 2FFP ~19.9% compared with GFP ~49.8% when a 1 ms duration pre-stress was applied with V_ds = 300 V in the OFF-state. Because of the discontinuous FP structure, more electric field peaks appear at the edge of the FFP stacks, which leads to a higher BV of ~454.4 V compared to the GFP ~394.3 V and the basic devices ~57.6 V. Moreover, the 2FFP structure performs lower a parasitic capacitance of C_gs = 1.03 pF and C_gd = 0.13 pF than those of the GFP structure (i.e., C_gs = 1.89 pF and C_gd = 0.18 pF). Lower parasitic capacitances lead to a much higher cut-off frequency (f_t) of 46 GHz and a maximum oscillation frequency (f_max) of 130 GHz than those of the GFP structure (i.e., f_t = 27 GHz and f_max = 93 GHz). These results illustrate the superiority of the 2FFP structure for RF GaN HEMT and open up enormous opportunities for integrated RF GaN devices.

In this work, a dramatic reduction in current collapse is achieved in GaN-based high-electron-mobility transistors (HEMTs) using dual-layer SiNx stressor passivation (DSSP), and the related mechanism is proposed. The SiNx compression neutralizes the inherent piezo polarization caused by the lattice mismatch at the heterojunction and effectively mitigates the peak electric field crowding at the drain-side gate edge, as supported by technology computer-aided design simulation. Thus, the inverse piezoelectric effect is suppressed and the trapped charge density is reduced under high electrical stress. As a result, the current collapse effect can be significantly restrained. Upon pulsing (Vg = −6 and Vds = 20 V), the device with DSSP exhibits a negligible current collapse (∼3%), which is significantly lower than the baseline device (∼34%). Moreover, it shows a one-order-of-magnitude reduction in gate leakage and a significant enhancement in gate stability. These results prove that the DSSP process is an attractive technique to facilitate high-reliability GaN-on-Si HEMTs.

In this work, we present the novel application of SiN_x stress-engineering techniques for the suppression of short-channel effects in AlGaN/GaN high-electron-mobility transistors (HEMTs), accompanied by a comprehensive analysis of the underlying mechanisms. The compressive stress SiN_x passivation significantly enhances the barrier height at the heterojunction beneath the gate, maintaining it above the quasi-Fermi level even as V_ds rises to 20 V. As a result, in GaN devices with a gate length of 160 nm, the devices with compressive stress SiN_x passivation exhibit significantly lower drain-induced barrier lowering (DIBL) factors of 2.25 mV/V, 2.56 mV/V, 4.71 mV/V, and 3.84 mV/V corresponding to drain bias voltages of 5 V, 10 V, 15 V, and 20 V, respectively. Furthermore, as V_ds increases, there is an insignificant degradation in transconductance, subthreshold swing, leakage current, or output conductance. In contrast, the devices with stress-free passivation show relatively higher DIBL factors (greater than 20 mV/V) and substantial degradation in pinch-off performance and output characteristics. These results demonstrate that the SiN_x stress-engineering technique is an attractive technique to facilitate high-performance and high-reliability GaN-based HEMTs for radio frequency (RF) electronics applications.

In this work, a normally-OFF $\beta $ -Ga2O3 MOSFET enabled by charge trapping layer (CTL) is demonstrated for the first time. The CTL consists of Al:HfO $_{x} 1$ :5 and the tunneling barrier (TB) is Al2O3/HfOx/Al2O3 stack. The developed Ga2O3 MOSFET exhibits a wide ${V}_{\text {th}}$ tuning range to normally-OFF operation and a long-lasting retention characteristic of −0.3 V (ten years). The device obtains a breakdown voltage (BV) of 1815 V, showing high reverse blocking capability based on the proposed CTL technique. ${I}$ – ${V}$ and ${C}$ – ${V}$ analyses are carried out under various temperatures to study the mechanism and explore the charge trapping and de-trapping processes. The results indicate a promising method to achieve E-mode operation for Ga2O3 MOSFET with low charge loss and stable ${V}_{\text {th}}$ .

This study optimizes the CuO_x/Ga₂O₃ heterojunction diodes (HJDs) by tailoring the structural parameters of CuO_x layers. The hole concentration in the sputtered CuO_x was precisely controlled by adjusting the Ar/O₂ gas ratio. Experimental investigations and TCAD simulations were employed to systematically evaluate the impact of the CuO_x layer dimension and hole concentration on the electrical performance of HJDs. The results indicate that increasing the diameter dimension of the CuO_x layer or tuning the hole concentration to optimal values significantly enhances the breakdown voltage (V_B) of single-layer HJDs by mitigating the electric field crowing effects. Additionally, a double-layer CuO_x structure (p⁺ CuO_x/p⁻ CuO_x) was designed and optimized to achieve an ideal balance between the V_B and specific on-resistance (R_on,sp). This double-layer HJD demonstrated a high V_B of 2780 V and a low R_on,sp of 6.46 mΩ·cm², further yielding a power figure of merit of 1.2 GW/cm². These findings present a promising strategy for advancing the performance of Ga₂O₃ devices in power electronics applications.

A robust Au-free p-type ohmic contact process with ultralow contact resistivity is developed on p-GaN/AlGaN/GaN, which demonstrates the potential of GaN CMOS to be compatible with Si CMOS process lines. A novel metal stack of Mg/Ni/Pt is designed, and ultralow contact resistivity of 8 Ω·mm (1.0×10 ^-5 Ω·cm ² ) is achieved. It is revealed that the Ga vacancies on the p-GaN surface induced by Ni, and the Ni ₂ O ₃ embed in the decomposed p-GaN are key to forming stable low resistivity ohmic contact.