This study focuses on the effect of the substrate temperature (T_S) on the quality of VO₂ thin films prepared by DC magnetron sputtering. T_S was varied from 350 to 600 °C and the effects on the surface morphology, microstructure, optical and electrical properties of the films were investigated. The results show that T_S below 500 °C favors the growth of V₂O₅ phase, whereas higher T_S (≥500 °C) facilitates the formation of the VO₂ phase. Optical characterization of the as-prepared VO₂ films displayed a reduced optical transmittance ($\tilde{T}$) across the near-infrared region (NIR), reduced phase transition temperature (T_t), and broadened hysteresis width (ΔH) through the phase transition region. In addition, a decline of the luminous modulation $(\mathsf{\Delta }{\tilde{T}}_{\mathrm{lum}})$ and solar modulation ($\mathsf{\Delta }{\tilde{T}}_{\mathrm{sol}}$) efficiencies of the as-prepared films have been determined. Furthermore, compared with the high-quality films reported previously, the electrical conductivity (σ) as a function of temperature (T) reveals reduced conductivity contrast (Δσ) between the insulating and metallic phases of the VO₂ films, which was of the order of 2. These outcomes indicated the presence of defects and unrelaxed lattice strain in the films. Further, the comparison of present results with those in the literature from similar works show that the preparation of high-quality films at T_S lower than 650 °C presents significant challenges.

In this work, VO₂ thin films were deposited on Si wafers (onto (100) surface) by DC magnetron sputtering under different cathode bias voltages. The effects of substrate biasing on the structural and optical properties were investigated. The results show that the metal–insulator transition (MIT) temperature of VO₂ thin films can be increased up to 14 K by applying a cathode bias voltage, compared to deposition conditions without any bias. The decrease in the transition efficiency and increase in the transition temperature are attributed to the enlarged grain size, increased defects, and the residual stress in the VO₂ thin films induced by biasing. The optical transmittance measurements for different thickness films indicate an attenuation coefficient of 3.1 × 10⁷ m⁻¹ at 2000 nm or an extinction coefficient of 4.9 in the metal phase. The optical transmittance vs wavelength characteristics point to an indirect bandgap of 0.6 ± 0.05 eV and significant scattering in the bulk and/or at the interface.

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (T_L), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. T_L was indirectly controlled by the heatsink temperature (T_S). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at T_L of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the T_L temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the T_L temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s.

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single cell design. In this paper the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates of stacked-transistor flip-flops are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high performance and radiation tolerant cells using the CnRx construct.

Research on single event effects (SEEs) is significant to the design and manufacture of modern electronic devices. By applying two photon absorption (TPA) ultra-fast pulsed lasers, extra electron-hole pairs (EHPs) are generated in a desired location on a chip, simulating the process that could occur in the circuit by energetic particles. In this study, a SEE sensitivity mapping system is described which uses this method to generate real-time sensitivity maps for various electronic devices. The system hardware includes an attenuator to control the energy, a Pockels cell as a fast-optical switcher and a mirror–mirror module to project the laser beam into a certain location. The system software developed for this application controls the laser system, automatically generates sensitivity maps, communicates with the testing devices and logs the SEE results. The two main features of this laser mapping system are: high scanning velocity for large area scanning (about 1 × 1 mm) and high spatial resolution for small area scanning (about 1 × 1 μm). To verify this mapping system, sensitivity maps were generated for static random access memory (SRAM) built with 65 nm technology and for commercial operational amplifiers (op-amps). The achieved sensitivity maps were compared with circuitry analysis and laser testing results, confirming this mapping system to be effective.