Dynamic random access memory (DRAM) bits can be erroneously flipped when the row near the error bits is repeatedly accessed with the activate and precharge commands in a process called row hammering. The trap at an Si–SiO ₂ interface has been previously reported as the leading cause of such errors. The number of row hammering required for flipping bits initially decreases and then saturates with the increases in the row precharge time ( $t_{\mathrm {RP}}$ ). The DRAM timing parameter is the time interval between an activate command and a precharge command. This study uses the saturation $t_{\mathrm {RP}}$ to estimate the electron emission time of the trap associated with a DRAM bit error. During $t_{\mathrm {RP}}$ time, the traps at the Si–SiO ₂ interface emit the trapped electrons. There are more chances of emission as $t_{\mathrm {RP}}$ increases, and less row hammering is needed. The emission time of a trapped electron is experimentally measured herein using commercial DDR4 components. The components are irradiated with gamma rays to induce the interface traps. The trap characteristics are then extracted without requiring an additional measurement setup with a device-level preparation. The trap energies with respect to the mid-band at the Si–SiO ₂ interface are 0.118–0.280 eV. The trap energies are distributed within approximately 5.6 kT energies at room temperature.

Advanced memories are designed using smaller geometries and lower voltages. This enables larger levels of integration and reduced power consumption, but makes memories more prone to suffer multibit soft errors. In this scenario, scrubbing is a fundamental technique to avoid the accumulation of errors, which would lead to a failure of the system. Scrubbing is usually implemented in advanced memories. However, when the percentage of multibit soft errors is significant, the scrubbing sequence (the order in which the memory is scrubbed) becomes important for the reliability of the system. In this paper, a new procedure to perform scrubbing is presented, which offers a significant improvement in the reliability. In the presence of multiple cell upsets, the mean time to failure could be doubled with respect to the traditional approach.

A memory fault model (FM) is an abstraction of the physical mechanism of memory failure. When the physical failure mechanisms are not fully represented in FMs, the coverage of the FMs can be different from that of the failure mechanisms. However, it is impractical (or impossible) to model every electrical aspect of the failure mechanisms with one or more FMs. This problem has become even worse with emerging technologies. Thus, in this study, the fault coverage (FC) consequences are investigated when the physical memory characteristics are not properly linked to the FMs or even test algorithms. Three physical characteristics were considered for this exploration: electrical masking, address scrambling, and electrical neighborhoods. To this end, memory fault simulations were performed, and the test algorithms were re-evaluated in terms of FC. Simulations were performed on the 1 kB area of the example SRAM model; three classes of FMs (56 static faults (SFs), 126 dynamic faults (DFs), and 192 neighborhood pattern-sensitive faults (NPSFs)) were simulated for FC evaluation; and March MSS, March MD2, and March 12N were used to re-evaluate the FCs of SFs, DFs, and NPSFs, respectively. From the simulation results, we observed the negative impact of physical characteristics on FC. When masking was considered, FC reductions of 10.72% SFs and 9.52% DFs were observed; when address scrambling was not available, an FC reduction of 80.21% NPSFs was observed. Finally, considering electrical neighborhood changes depending on the physical memory structure, an FC reduction of 41.67% NPSFs was observed.

High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integration with heterogeneous chips. The effects of the temperature at the base logic die (T_L), and the refresh interval at the stacked DRAM dies, were experimentally investigated by counting the dynamic retention errors in the eight channels in an HBM2. T_L was indirectly controlled by the heatsink temperature (T_S). The lognormal distribution represents the distribution of the cell counts with varying refresh times. All Z-magnitudes (multiples of the distribution standard deviation) over the various refresh cycle times (RCTs) up to 2.045 s in a single channel at T_L of 70 °C appeared below 4.4, which means that the error bits belong to the tail distribution. The Z-differences in the eight channels were distinctively larger than the Z-differences of the same channels at a constant temperature, demonstrating that the temperature difference in the stacked dies resulted in larger Z-differences. The largest Z-difference was 0.091 for all the channels at an RCT of 1.406 s, which was approximately 4.82 times smaller than the Z-difference between the T_L temperatures of 70 °C and 80 °C in a single channel. The Z-difference between the T_L temperatures of 70 °C and 72 °C in a single channel was approximately the same as the Z-difference in all the channels at an RCT of 2.045 s.

This paper shows that an intermittent AC coupling defect occurring in a DDR4 data channel will cause more intermittent errors in DDR4, compared to such defect in DDR3. The intermittent AC coupling defect occurs due to intermittent fracture in DDR4 package solder ball. The defect causes DC offset in DDR4, which shifts the data signal or data eye and results in DDR4 data channel failure. The DC offset occurs due to the asymmetric nature of pseudo open drain termination scheme. DDR4 data channel response is compared with DDR3 channel. It is shown that pseudo random binary sequence (PRBS) pattern will always cause failure for DDR4, but PRBS will only cause failure in DDR3 if the sequence of consecutive 0's or 1's in PRBS pattern is long enough to cause threshold violation. As a result there will be more intermittent errors in DDR4 compared to DDR3. The defect due to fracture in solder ball is modelled by an AC coupling capacitor. A 1nF AC coupling capacitor corresponding to a solder ball fracture of height about 1nm is used to show the difference between DDR4 and DDR3 response.