Three-dimensional (3-D) nanostructures have demonstrated enticing potency to boost performance of photovoltaic devices primarily owning to the improved photon capturing capability. Nevertheless, cost-effective and scalable fabrication of regular 3-D nanostructures with decent robustness and flexibility still remains as a challenging task. Meanwhile, establishing rational design guidelines for 3-D nanostructured solar cells with the balanced electrical and optical performance are of paramount importance and in urgent need. Herein, regular arrays of 3-D nanospikes (NSPs) were fabricated on flexible aluminum foil with a roll-to-roll compatible process. The NSPs have precisely controlled geometry and periodicity which allow systematic investigation on geometry dependent optical and electrical performance of the devices with experiments and modeling. Intriguingly, it has been discovered that the efficiency of an amorphous-Si (a-Si) photovoltaic device fabricated on NSPs can be improved by 43%, as compared to its planar counterpart, in an optimal case. Furthermore, large scale flexible NSP solar cell devices have been fabricated and demonstrated. These results not only have shed light on the design rules of high performance nanostructured solar cells, but also demonstrated a highly practical process to fabricate efficient solar panels with 3-D nanostructures, thus may have immediate impact on thin film photovoltaic industry.

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High ${f}_{\text {T}}$ and ${f}_{\text {max}}$ IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on–off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage ( ${V}_{\text {DD}}$ ). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the ${V}_{\text {TH}}$ tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

The emerging applications of silicon photonics in free space, such as LiDARs, free‐space optical communications, and quantum photonics, urge versatile emission shaping beyond the capabilities of conventional grating couplers. In these applications, silicon photonic chips deliver free‐space emission to detect or manipulate external objects. Light needs to emit from a silicon photonic chip to the free space with specific spatial modes, which produce focusing, collimation, orbital angular momentum, or even holographic projection. A platform that offers versatile shaping of free‐space emission, while maintaining the CMOS compatibility and monolithic integration of silicon photonics is in pressing need. Here we demonstrate a platform that integrates metasurfaces monolithically on silicon photonic integrated circuits. The metasurfaces consist of amorphous silicon nanopillars evanescently coupled to silicon waveguides. We demonstrate experimentally diffraction‐limited beam focusing with a Strehl ratio of 0.82. The focused spot can be switched between two positions by controlling the excitation direction. We also realize a meta‐hologram experimentally that projects an image above the silicon photonic chip. This platform can add a highly versatile interface to the existing silicon photonic ecosystems for precise delivery of free‐space emission.