The rapid development in wind power comes with new technical challenges. Reliable and accurate wind power forecast is of considerable significance to the electricity system’s daily dispatching and production. Traditional forecast methods usually utilize wind speed and turbine parameters as the model inputs. However, they are not sufficient to account for complex weather variability and the various wind turbine features in the real world. Inspired by the excellent performance of convolutional neural networks (CNN) in computer vision, we propose a novel approach to predicting short-term wind power by converting time series into images and exploit a CNN to analyze them. In our approach, we first propose two transformation methods to map wind speed and precipitation data time series into image matrices. After integrating multi-dimensional information and extracting features, we design a novel CNN framework to forecast 24-h wind turbine power. Our method is implemented on the Keras deep learning platform and tested on 10 sets of 3-year wind turbine data from Hangzhou, China. The superior performance of the proposed method is demonstrated through comparisons using state-of-the-art techniques in wind turbine power forecasting.

Pedestrian detection has attracted great research attention in video surveillance, traffic statistics, and especially in autonomous driving. To date, almost all pedestrian detection solutions are derived from conventional framed-based image sensors with limited reaction speed and high data redundancy. Dynamic vision sensor (DVS), which is inspired by biological retinas, efficiently captures the visual information with sparse, asynchronous events rather than dense, synchronous frames. It can eliminate redundant data transmission and avoid motion blur or data leakage in high-speed imaging applications. However, it is usually impractical to directly apply the event streams to conventional object detection algorithms. For this issue, we first propose a novel event-to-frame conversion method by integrating the inherent characteristics of events more efficiently. Moreover, we design an improved feature extraction network that can reuse intermediate features to further reduce the computational effort. We evaluate the performance of our proposed method on a custom dataset containing multiple real-world pedestrian scenes. The results indicate that our proposed method raised its pedestrian detection accuracy by about 5.6–10.8%, and its detection speed is nearly 20% faster than previously reported methods. Furthermore, it can achieve a processing speed of about 26 FPS and an AP of 87.43% when implanted on a single CPU so that it fully meets the requirement of real-time detection.

Edge devices employing federated learning encounter several obstacles, including (1) the non-independent and identically distributed (Non-IID) nature of client data, (2) limitations due to communication bottlenecks, and (3) constraints on computational resources. To surmount the Non-IID data challenge, personalized federated learning has been introduced, which involves training tailored networks at the edge; nevertheless, these methods often exhibit inconsistency in performance. In response to these concerns, a novel framework for personalized federated learning that incorporates adaptive pruning of edge-side data is proposed in this paper. This approach, through a two-staged pruning process, creates customized models while ensuring strong generalization capabilities. Concurrently, by utilizing sparse models, it significantly condenses the model parameters, markedly diminishing both the computational burden and communication overhead on edge nodes. This method achieves a remarkable compression ratio of 3.7% on the Non-IID dataset FEMNIST, with the training accuracy remaining nearly unaffected. Furthermore, the total training duration is reduced by 46.4% when compared with the standard baseline method.

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm², which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm². The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency.