The rapid development in wind power comes with new technical challenges. Reliable and accurate wind power forecast is of considerable significance to the electricity system’s daily dispatching and production. Traditional forecast methods usually utilize wind speed and turbine parameters as the model inputs. However, they are not sufficient to account for complex weather variability and the various wind turbine features in the real world. Inspired by the excellent performance of convolutional neural networks (CNN) in computer vision, we propose a novel approach to predicting short-term wind power by converting time series into images and exploit a CNN to analyze them. In our approach, we first propose two transformation methods to map wind speed and precipitation data time series into image matrices. After integrating multi-dimensional information and extracting features, we design a novel CNN framework to forecast 24-h wind turbine power. Our method is implemented on the Keras deep learning platform and tested on 10 sets of 3-year wind turbine data from Hangzhou, China. The superior performance of the proposed method is demonstrated through comparisons using state-of-the-art techniques in wind turbine power forecasting.

In the prognostics health management (PHM) of rotating machinery, the accurate identification of bearing fault is critical. In recent years, various deep learning methods can well identify bearing fault based on monitoring data. However, facing changing operating conditions and noise pollution, the accuracy of these algorithms decreases significantly, which makes the algorithms difficult in practical applications. To solve this problem, a novel capsule network based on wide convolution and multi-scale convolution (WMSCCN) is proposed for fault diagnosis. The proposed WMSCCN algorithm takes one-dimensional vibration signal as an input and no additional manual processing is required. In addition, the adaptive batch normalization (AdaBN) algorithm is introduced to further enhance the adaptability of WMSCCN under noise pollution and load changes. On generalization experiments under different loads, the proposed WMSCCN and WMSCCN-AdaBN algorithms achieve average accuracy rates of 96.44% and 97.44%, respectively, which is superior to other advanced algorithms. In the noise resistance experiment, the proposed WMSCCN-AdaBN can maintain a 92.3% diagnostic accuracy in a strong noise environment with a signal to noise ratio (SNR) = −4 dB, showing a very strong anti-noise ability. When the SNR exceeds 4 dB, the accuracy reaches 100%, indicating that the proposed algorithm has a very good accuracy at low noise levels. Two experiments have effectively verified the validity and generalizability of the proposed model.

This paper presents a compact vector quantizer based on the self-organizing map (SOM), which can fulfill the data compression task for high-speed image sequence. In this vector quantizer, we solve the most severe computational demands in the codebook learning mode and the image encoding mode by a reconfigurable complete-binary-adder-tree (RCBAT), where the arithmetic units are thoroughly reused. In this way, the hardware efficiency of our proposed vector quantizer is greatly improved. In addition, by distributing the codebook into the multi-parallel processing sub-blocks, our design obtains a high compression speed successfully. Furthermore, a mechanism of partial vector-component storage (PVCS) is adopted to make the compression ratio adjustable. Finally, the proposed vector quantizer has been implemented on the field programmable gate array (FPGA). The experimental results indicate that it respectively achieves a compression speed of 500 frames/s and a million connections per second (MCPS) of 28,494 (compression ratio is 64) when working at 79.8 MHz. Besides, compared with the previous scheme, our proposed quantizer achieves a reduction of 8% in hardware usage and an increase of 33% in compression speed. This means the proposed quantizer is hardware-efficient and can be used for high-speed image compression.

Recently, non-orthogonal multiple access (NOMA) has become prevalent in 5G communication. However, the traditional successive interference cancellation (SIC) receivers for NOMA still encounter challenges. The near-far effect between the users and the base stations (BS) results in a higher bit error rate (BER) for the SIC receiver. Additionally, the linear detection algorithm used in each SIC stage fails to eliminate the interference and is susceptible to error propagation. Consequently, designing a high-performance NOMA system receiver is a crucial challenge in NOMA research and particularly in signal detection. Focusing on the signal detection of the receiver in the NOMA system, the main work is as follows. (1) This thesis leverages the strengths of deep neural networks (DNNs) for nonlinear detection and incorporates the low computational complexity of the successive interference cancellation (SIC) structure. The proposed solution introduces a feedback deep neural network (FDNN) receiver to replace the SIC in signal detection. By employing a deep neural network for nonlinear detection at each stage, the receiver mitigates error propagation, lowers the BER in NOMA systems, and enhances resistance against inter-user interference (IUI). (2) We describe its algorithm flow and provide simulation results comparing FDNN and SIC receivers under MIMO-NOMA scenarios. The simulations clearly demonstrate that FDNN receivers outperform SIC receivers in terms of BER for MIMO-NOMA systems.

A three-dimensional (3D) image sensor based on Single-Photon Avalanche Diode (SPAD) requires a time-to-digital converter (TDC) with a wide dynamic range and fine resolution for precise depth calculation. In this paper, we propose a novel high-performance TDC for a SPAD image sensor. In our design, we first present a pulse-width self-restricted (PWSR) delay element that is capable of providing a steady delay to improve the time precision. Meanwhile, we employ the proposed PWSR delay element to construct a pair of 16-stages vernier delay-rings to effectively enlarge the dynamic range. Moreover, we propose a compact and fast arbiter using a fully symmetric topology to enhance the robustness of the TDC. To validate the performance of the proposed TDC, a prototype 13-bit TDC has been fabricated in the standard 0.18-µm complementary metal–oxide–semiconductor (CMOS) process. The core area is about 200 µm × 180 µm and the total power consumption is nearly 1.6 mW. The proposed TDC achieves a dynamic range of 92.1 ns and a time precision of 11.25 ps. The measured worst integral nonlinearity (INL) and differential nonlinearity (DNL) are respectively 0.65 least-significant-bit (LSB) and 0.38 LSB, and both of them are less than 1 LSB. The experimental results indicate that the proposed TDC is suitable for SPAD-based 3D imaging applications.

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm², which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.