Pedestrian detection has attracted great research attention in video surveillance, traffic statistics, and especially in autonomous driving. To date, almost all pedestrian detection solutions are derived from conventional framed-based image sensors with limited reaction speed and high data redundancy. Dynamic vision sensor (DVS), which is inspired by biological retinas, efficiently captures the visual information with sparse, asynchronous events rather than dense, synchronous frames. It can eliminate redundant data transmission and avoid motion blur or data leakage in high-speed imaging applications. However, it is usually impractical to directly apply the event streams to conventional object detection algorithms. For this issue, we first propose a novel event-to-frame conversion method by integrating the inherent characteristics of events more efficiently. Moreover, we design an improved feature extraction network that can reuse intermediate features to further reduce the computational effort. We evaluate the performance of our proposed method on a custom dataset containing multiple real-world pedestrian scenes. The results indicate that our proposed method raised its pedestrian detection accuracy by about 5.6–10.8%, and its detection speed is nearly 20% faster than previously reported methods. Furthermore, it can achieve a processing speed of about 26 FPS and an AP of 87.43% when implanted on a single CPU so that it fully meets the requirement of real-time detection.

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm², which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.