In a conventional bio-sensor, key signal features are acquired using Nyquist-rate analog-to-digital conversion without exploiting the typical bio-signal characteristic of sparsity in some domain (e.g., time, frequency, etc.). Compressed sensing (CS) is a signal processing paradigm that exploits this sparsity for commensurate power savings by enabling alias-free sub-Nyquist acquisition. In a severely energy constrained sensor, CS also eliminates the need for digital signal processing (DSP). A fully-integrated low-power CS analog front-end (CS-AFE) is described for an electrocardiogram (ECG) sensor. Switched-capacitor circuits are used to achieve high accuracy and low power. Implemented in 0.13 μm CMOS in 2×3 mm², the prototype comprises a 384-bit Fibonacci-Galois hybrid linear feedback shift register and 64 digitally-selectable CS channels with a 6-bit C-2C MDAC/integrator and a 10-bit C-2C SAR ADC in each. Clocked at 2 kHz, the total power dissipation is 28 nW and 1.8 μW for one and 64 active channels, respectively. CS-AFE enables compressive sampling of bio-signals that are sparse in an arbitrary domain.

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art.

The best beam steering directions are estimated through beam training, which is one of the most important and challenging tasks in millimeter-wave and sub-terahertz communications. Novel array architectures and signal processing techniques are required to avoid prohibitive beam training overhead associated with large antenna arrays and narrow beams. In this work, we leverage recent developments in true-time-delay (TTD) arrays with large delay-bandwidth products to accelerate beam training using frequency-dependent probing beams. We propose and study two TTD architecture candidates, including analog and hybrid analog-digital arrays, that can facilitate beam training with only one wideband pilot. We also propose a suitable algorithm that requires a single pilot to achieve high-accuracy estimation of angle of arrival. The proposed array architectures are compared in terms of beam training requirements and performance, robustness to practical hardware impairments, and power consumption. The findings suggest that the analog and hybrid TTD arrays achieve a sub-degree beam alignment precision with 66% and 25% lower power consumption than a fully digital array, respectively. Our results yield important design trade-offs among the basic system parameters, power consumption, and accuracy of angle of arrival estimation in fast TTD beam training.

This work proposes a new automatic model parameter selection approach for determining the optimal configuration of high-speed analog-to-digital converters (ADCs) using a combination of particle swarm optimization (PSO) and stochastic gradient descent (SGD) algorithm. The proposed hybrid method first initializes the PSO algorithm to search for optimal neural-network configuration via the particles moving in finite search space with coarse quantization. Using the PSO estimates, the SGD algorithm then finds the global optimum solution. The global search ability of the PSO algorithm and the local search ability of the SGD are thus exploited to determine an optimal solution that is close to the global optimum with reduced latency. Several experiments were constructed to optimize the non-linearities in Nyquist flash and pipeline ADC datasets to show that the neural networks trained by the PSO-SGD algorithm outperform the random search-based performance optimization. Comparative resource analysis of the proposed algorithm is also conducted against the state-of-the-art that highlights improved latencies and performance with similar area and implementation complexity.

Initial access in millimeter-wave (mmW) wireless is critical toward successful realization of the fifth-generation (5G) wireless networks and beyond. Limited bandwidth in existing standards and use of phase-shifters in analog/hybrid phased-antenna arrays (PAAs) are not suited for these emerging standards demanding low-latency direction finding. This work proposes a reconfigurable true-time-delay (TTD)-based spatial signal processor (SSP) with frequency-division beam training methodology and wideband beam-squint less data communications. Discrete-time delay compensated clocking technique is used to support 800-MHz bandwidth with a large unity-gain bandwidth ring-amplifier (RAMP)-based signal combiner. To extensively characterize the proposed SSP across different SSP modes and frequency–angle pairs, an automated testbed is developed using computer vision techniques that significantly speeds up the testing progress and minimizes possible human errors. Using seven levels of time-interleaving for each of the four antenna elements, TTD SSP has a delay range of 3.8 ns over 800 MHz and achieves unique frequency-to-angle mapping in the beam training mode with nearly 12-dB frequency-independent gain in the beamforming mode. The SSP is prototyped in 65-nm CMOS with an area of 1.98 mm $^2$ consuming only 29 mW excluding buffers. Furthermore, an error vector magnitude (EVM) of 7.3% is realized for 16-QAM modulation at a speed of 614.4 Mb/s.