The accuracy in electrical model parameters of solar photovoltaic (PV), such as photon current, the diode dark saturation current, series resistance, shunt resistance, and diode ideality factor, are desirable to predict the real performance characteristics of solar PV under varying environment conditions. First, this paper derives mathematical model of solar PV, in terms of two unknown, namely, series resistance and ideality factor. Then, using combination of analytical method, simulated annealing method, and derived model, a new parameter estimation technique has been proposed. Finally, performance indices, such as PV characteristics curve, relative maximum power error, root mean square deviation, and normalized root mean square deviation are estimated for the various solar PV panels, using proposed and existing methods, to reveal the effectiveness of the proposed method. Also, experimental data have been considered for the validation. Finally, through the comparative analysis of the results, it is revealed that the proposed method offers solar PV characteristics more closer to the real characteristics than the other existing methods.

The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO $_{\text{2}}$ interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.

Two different equations for the current through voltage-dependent capacitances are used in the literature. One equation is obtained from the time derivative of charge that is considered as capacitance–voltage product: dQ/dt=d[C(V)V]/dt=C(V)[dV/dt]+V[dC(V)/dt]. In the second equation, the term V[dC(V)/dt] does not exist: dQ/dt= C(V)[dV/dt]. This paper clears the ongoing confusion caused by the difference between these two equations. We use the voltage-dependent parasitic capacitance of a commercial Schottky diode in reverse bias mode to test experimentally both equations. The result is that it is incorrect to add the term V[dC(V)/dt] in the first equation with the measured capacitance. We also perform a theoretical analysis, which shows that the differential capacitance, C(V)=dQ/dV, in the correct current equation corresponds to the physical parameters of the diode capacitance.

The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and drain-to-source voltage during the switching intervals. However, this technique does not separate the switching power due to the resistance of the MOSFET channel and due to the parasitic capacitances. In this paper, we propose a measurement method to extract the power dissipation due to the parasitic capacitances of a MOSFET, providing useful information for device selection and for the design of efficient power electronic systems. The proposed method is demonstrated on a basic boost converter. The proposed method shows that the existing method underestimates the turn-On losses by 41% and overestimates the turn-Off losses by 35%.

A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.