The suboptimal performance and low channel-carrier mobility of silicon carbide (SiC) power MOSFETs are attributed to a high density of oxide traps near the 4H-SiC/SiO $_{\text{2}}$ interface. In this article, a commercial 1200-V SiC trench MOSFET has been compared with a planar MOSFET obtained from the same manufacturer. We employed a newly developed integrated-charge method to quantify the near-interface traps (NITs). The results reveal that, at operating gate voltages, 15% of the total channel electrons were trapped for longer than 500 ns in the planar MOSFET compared to 9% in the trench MOSFET.

The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL 3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL 3 model. The advantage of the proposed approach to use the MOSFET LEVEL 3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL 3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and drain-to-source voltage during the switching intervals. However, this technique does not separate the switching power due to the resistance of the MOSFET channel and due to the parasitic capacitances. In this paper, we propose a measurement method to extract the power dissipation due to the parasitic capacitances of a MOSFET, providing useful information for device selection and for the design of efficient power electronic systems. The proposed method is demonstrated on a basic boost converter. The proposed method shows that the existing method underestimates the turn-On losses by 41% and overestimates the turn-Off losses by 35%.

This brief presents direct electrical measurement of active defects in the strong-accumulation region of N-type 4H-SiC MOS capacitors, which corresponds to the strong-inversion region of N-channel MOSFETs. The results demonstrate the existence of an active defect in the gate oxide, located very close to the SiC surface, with localized energy levels between 0.13 eV and 0.23 eV above the bottom of the conduction band. The observed spatial and energy localizations indicates that this is a well-defined defect.

A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.

The parasitic capacitances of semiconductor power devices that contribute to the switching losses are voltage-dependent, which can make calculations of their stored energy difficult. Typically, manufacturers will provide effective capacitance values to aid in circuit design and component selection. However, stored energy calculations using these effective capacitor values are erroneous. In this paper, we derive a new equation for the stored energy in the voltage-dependent capacitance associated with a semiconductor depletion region, such as in a diode or transistor. In particular, we show that the ½ term in ½CV $^2$ should be replaced by a new term γ, which depends on the device structure. By applying our proposed method to several commercial diodes and transistors, we show that it matches the measured data much better than using the effective capacitances. The proposed method will enable better power circuit design by improving the accuracy of stored energy calculations.