This letter presents a high-performance architecture of a novel first-order polynomial convolution interpolation for digital image scaling. A better quality of interpolation is achieved by using higher order model that requires complex computations. The kernel of the proposed method is built up of first-order polynomials and approximates the ideal sinc-function in the interval [-2, 2]. The proposed architecture reduces the computational complexity of generating weighting coefficients and provides a simple hardware architecture design and low computation cost, and easily meets real-time requirements. The architecture is implemented on the Virtex-II FPGA, and the high-performance very-large-scale integration architecture has been successfully designed and implemented with the TSMC 0.13 μm standard cell library. The simulation results indicate that the interpolation quality of the proposed architecture is mostly better than cubic convolution interpolations, and is able to process varying-ratio image scaling for high-definition television in real-time.

This paper presents a channel-wise average pooling and one dimension pixel-shuffle architecture for a denoising autoencoder (CPDAE) design that can be applied to efficiently remove electrode motion (EM) artifacts in an electrocardiogram (ECG) signal. The three advantages of the proposed design are as follows: (1) In the skip connection layer, less memory is needed to transfer the features extracted by the neural network; (2) Pixel shuffle and pixel unshuffle techniques with point-wise convolution are used to effectively reserve the key features generated from each layer in both the encoder and decoder; (3) Overall, fewer parameters are required to reconstruct the ECG signal. This paper describes three deep neural network models, namely CPDAE_Lite, CPDAE_Regular, and CPDAE_Full, which support various computational capacity and hardware arrangements. The three proposed structures involve an encoder and decoder with six, seven, and eight layers, respectively. Furthermore, the CPDAE_Lite, CPDAE_Regular, and CPDAE_Full structures require fewer multiply-accumulate operations—355.01, 56.96, and 14.69 million, respectively—and less parameter usage—2.69 million, 149.7 thousand, and 55.5 thousand, respectively. To evaluate the denoising performance, the MIT–BIH noise stress test database containing six signal-to-noise ratios (SNRs) of noisy ECGs was employed. The results demonstrated that the proposed models had a higher improvement of SNR and lower percentage root-mean-square difference than other state-of-the-art methods under various conditions of SNR.

The modeling of human body kye-points is the most significant aspect of pose estimation appropriately. Computer vision algorithm identifies human pose, body-movement, and action in many ways. Most of the previous works taken advantage for finding accuracy or efficiency in terms of speed. However, many techniques suffer for intensive computational demands with low-latency or higher proceeding speed. We have designed a unique approach for single-person pose estimation and action recognition which is well suited for fitness application and mobility activities. The proposed framework has been developed with a base network that provides an initial pose to further refinement through Intensive Feature Consistency (IFC) network. The IFC network enforces high-level constraints on the global body intensity correction and local body part adjustments. The proposed module reduces the impact of body joint movement diversity by interpreting long-term consistent view. We have illustrated the effectiveness of proposed framework through pose estimation accuracy improvement with two benchmark datasets. Which is specified state-of the- art performance of IFC network under the required real-time processing speed on the CPU platform. The IFC network has improved 99.1% of PCK body and 94.7% of PCK torso accuracy under 31 FPS, which is comparatively higher than the existing work.

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

This paper presents a novel low-complexity impedance calculation based on a compact recursive discrete Fourier transform (RDFT) for electrical impedance spectroscopy (EIS) system design. Compared to a traditional fast Fourier transform, an arbitrary-length RDFT is not limited by the power-of-two transform length. By choosing a suitable integer ratio of the desired frequency/frequency resolution, the spectrum leakage can be significantly reduced by 4-Hz resolution per bin, which enables a lower magnitude relative error (MRE) and a phase absolute error (PAE) in impedance calculations. Here, the practical measurement results show that the maximum MRE and PAE are below 0.1% and 0.5°, respectively, making this approach superior to previously reported ones. Compared with the state-of-the-art Goertzel filter-based EIS system, the proposed method provides more frequency bins (+43.75%) within the same frequency band, and the operations in terms of square root, division, and arctangent are drastically reduced by 50%, 33%, and 50%, respectively. In addition, the proposed system only costs $474 USD and can serve as a suitable solution for various EIS applications in the future.

This study presents a novel hybrid algorithm merging Recursive Discrete Fourier Transform (RDFT) and Fast Fourier Transform (FFT) to meet the demands of Electrochemical Impedance Spectroscopy (EIS) applications. It particularly addresses scenarios where users need to calculate a reduced number or a variable quantity of frequency bins. By offering the flexibility for users to choose either RDFT or FFT based on their specific requirements, the algorithm overcomes the limitation encountered in traditional impedance calculation methods, where the FFT transform length is constrained to being a power of two. To ensure more precise observation of the Device Under Test (DUT) impedance spectrum, we set the sampling rate (Fs) and transform length (N) to 40960, achieving a frequency resolution of 1Hz. Unlike the traditional Radix-2 FFT method, the proposed hybrid algorithm eliminates the need for zero padding to supplement the signal to 65536 points. Consequently, the overall computation involves 1,163,264 multiplications and 2,359,296 additions, marking a notable reduction of 44.52% in multiplications and 43.94% in additions compared to the traditional radix-2 FFT method’s 2,097,152 multiplications and 4,194,304 additions. In order to validate measurement accuracy, experiments were performed using six pure resistors and two RC circuits. The RDFT-based impedance calculations, after averaging all measurements, resulted in magnitude relative error (MRE) and phase absolute error (PAE) values below 0.11% and 0.21°, respectively. Likewise, impedance calculations utilizing the hybrid algorithm showcased even greater precision, with MRE below 0.06% and PAE below 0.09°. These findings highlight the superior accuracy and streamlined complexity provided by the proposed system. For hardware implementation, the system costs only $352 USD, offering a cost-effective solution for various high-precision EIS measurement applications.