Peisen cheng

Mr. Peisen cheng

Key Lab of Semiconductor Materials Science, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
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Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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28 January 2021 in Electronics
Verified
Journal Article
Open access
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Peisen chengPeisen cheng
Peisen cheng
QWQuan Wang
Quan Wang
WLWei Li
Wei Li
YJYeting Jia
Yeting Jia
ZLZhichao Liu
Zhichao Liu
XWXiaoliang Wang
Xiaoliang Wang
This paper proposes a broadband asymmetrical monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) using 0.25-μm gallium-nitride process with a compact chip size of 2.37 × 1.86 mm2 for 5G communication. It adopts an unequal Wilkinson’s power divider with a ratio of 2.5:1, where 71.5% of the total power is transferred to the main amplifier for higher gain. Different input matching networks are used to offset phase difference while completing impedance conversion. This design also applies a novel topology to solve the problem of large impedance transformer ratio (ITR) in conventional DPA, and it optimizes the ITR from 4:1 to 2:1 for wider band. Moreover, most of the components of the DPA including power divider and matching networks use lumped inductors and capacitors instead of long transmission line (TL) for a smaller space area. The whole circuit is designed and simulated using Agilent’s advanced design system (ADS). The simulated small-signal gain of DPA is 8–11 dB and the saturation output power is more than 39.5 dBm with 800 MHz band from 4.5 GHz to 5.3 GHz. At 6-dB output power back-off, the DPA demonstrates 38–41.3% power added efficiency (PAE), whereas 44–54% PAE is achieved at saturation power.