Analog and digital SiPMs have revolutionized the field of radiation instrumentation by replacing both avalanche photodiodes and photomultiplier tubes in many applications. However, multiple applications require greater performance than the current SiPMs are capable of, for example timing resolution for time-of-flight positron emission tomography and time-of-flight computed tomography, and mitigation of the large output capacitance of SiPM array for large-scale time projection chambers for liquid argon and liquid xenon experiments. In this contribution, the case will be made that 3D photon-to-digital converters, also known as 3D digital SiPMs, have a potentially superior performance over analog and 2D digital SiPMs. A review of 3D photon-to-digital converters is presented along with various applications where they can make a difference, such as time-of-flight medical imaging systems and low-background experiments in noble liquids. Finally, a review of the key design choices that must be made to obtain an optimized 3D photon-to-digital converter for radiation instrumentation, more specifically the single-photon avalanche diode array, the CMOS technology, the quenching circuit, the time-to-digital converter, the digital signal processing and the system level integration, are discussed in detail.

Retinal implants aim to partially restore vision to patients suffering from blindness caused by age-related macular degeneration (AMD) or retinitis pigmentosa (RP). Up until now, most prostheses were powered using an inductive link coupled with cables penetrating through the eyeball. Although they efficiently power the implant, they limit long-term reliability and cause postoperative complications. A fully wireless near-infrared power and data link entering the eye through the pupil alleviates these issues but limits the available power and causes energy supply interruptions during blinking. This article presents a retinal implant ASIC architecture optimized for optical operation despite these constraints. It contains 288 individually controlled electrode drivers, each connected to electrode pads with a pitch of 150 μm. A digital controller with a stateless communication scheme allows flexible stimulation sequences and is capable of restoring stimulation within 3 ms after an eye blink. The prototype was fabricated using a CMOS 65-nm low-power technology and occupies an area of 2.8 × 3.1 mm ² with a static power consumption of 3.1 mW.

When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports on a characterization and monitoring platform dedicated to SPAD testing at die and wafer level, in the context of a 3D SPAD technology development. The platform relies on a dedicated integrated circuit made in a standard CMOS technology and used in different configurations from a prototype printed circuit board (die-level testing) to active probe cards (wafer-level mapping). The platform gives full access to SPAD characteristics in Geiger mode such as the dark noise, photon detection efficiency and timing resolution. The integrated circuit and its configuration are described in detail as well as results obtained on different SPAD test structures. In particular, the dark count rate mapping demonstrates the benefits of testing SPADs at wafer level at the R&D stage.

A new trend in large area noble liquid experiments is to measure the scintillation light with photodetectors and their electronics inside the active volume. Compared to the typical approach of using silicon photomultipliers (SiPM) with an analog readout chain leading to an analog-to-digital converter, this paper presents a new 3D photon-to-digital converter (PDC) readout that takes advantage of the binary nature of the single-photon avalanche diodes (SPAD). The readout contains 4096 pixels over 25 mm², each including a 3D bonding pad and a quenching circuit. The readout features three different outputs: a fast flag to get the timestamp of each event from an external time-to-digital converter, a digital sum to retrieve the number of pixels triggered during an event, and an analog monitor to generate an analog SiPM-like output. The analog monitor is also used to validate the two former digital outputs. The readout also includes 61 2D CMOS SPADs for validation purpose prior to the final 3D integration with SPADs custom made according to our design by Teledyne DALSA (Bromont, Canada). As a first system integration toward large-area detector applications, a mini-tile of 2 × 2 readouts has been developed to test all the functionalities. The measured single-photon timing resolution ranges from 72 to 93 ps FWHM across the mini-tile SPAD channels population (i.e. 4 × 61 channels). The flag timing resolution is below 95 ps RMS, which includes the contribution of the optimized flag H-tree but also an additional trigger tree that replaces the 3D SPAD array at this stage of development. Once bonded with the 3D SPADs, the trigger tree won't be required to measure the flag timing resolution. With the removed contribution of the trigger tree, the estimated flag timing resolution should be below 45 ps RMS. The extent of the benefits of the digital sum output depend on the application, and this paper focuses on two cases. First, a low-power coincidence scheme such as required by the nEXO liquid xenon experiment, leading to a power consumption as low as 140 μW per PDC. With a finer sampling of the scintillation light such as required for pulse shape discrimination in liquid argon, the power consumption remains below 100 μW per PDC. Overall, this readout is designed as a replacement for a typical analog SiPM chain, without compromise on the performances.

This paper reports on a wafer-level test platform for Single-Photon Avalanche Diodes (SPADs) manufactured at Teledyne DALSA (Canada) and designed by Université de Sherbrooke. The platform enables in-foundry end-of-process active testing of SPADs in Geiger-mode, thanks to a dedicated integrated circuit and probe card installed on a wafer prober.

We present an integrated single-photon detection device custom designed for quantum key distribution (QKD) with time-bin encoded single photons. We implemented and demonstrated a prototype photon-to-digital converter (PDC) that integrates an 8 × 8 single-photon avalanche diode (SPAD) array with on-chip digital signal processing built in TSMC 65 nm CMOS. The prototype SPADs are used to validate the QKD functionalities with an array of time-to-digital converters (TDCs) to timestamp and process the photon detection events. The PDC uses window gating to reject noise counts and on-chip processing to sort the photon detections into respective time-bins. The PDC prototype achieved a 22.7 ps RMS timing resolution and demonstrated operation in a time-bin setup with 158 ps time-bins at an optical wavelength of 410 nm. This PDC can therefore be an important building block for a QKD receiver and enables compact and robust time-bin QKD systems with imaging detectors.