Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

Resistive random access memory device (RRAM) has been widely used in various novel circuit systems, such as memory, artificial intelligence, and neural networks, due to its unique memory characteristics. However, there are very few studies focusing on analytic modeling of RRAM. In this work, modeling for solving analytic approximate solution to the state variable of RRAM, based on the proposed Multistage Homotopy Analysis Method (MuHAM), is proposed. Different from traditional HAM, the time span under consideration is divided into many subintervals, then the convergence control parameter in each subinterval is optimized to achieve high approximation accuracy. By simulating and comparing the obtained analytic solutions with solutions solved by other traditional homotopy-based modeling methodologies and by numerical analyses, we verified that MuHAM has higher Quality Factor (introduced to evaluate the model accuracy and computational cost comprehensively), hence improving the simulation efficiency. Besides the classical Hewlett-Packard (HP) RRAM, some current RRAMs are also verified. MuHAM also has the advantages of enabling both qualitative and quantitative analyses, and immunity to convergence issues. It is particularly suitable for the analytic modeling of the other novel memory devices having strong nonlinearity.

Scan testing is the key technology in the design for test of integrated circuit. For existing scan testing methods, the scan-in for test stimuli requires many clock cycles, which is one of the main restrictions of scan testing. To shorten the scan testing time of an integrated circuit, a novel test stimulus scan-in method was proposed in this study. First, scan chains, test stimuli, and test responses were grouped according to a fixed data width. Second, logic XOR calculation results of test response and test stimuli were coded according to the bit width of each group. The corresponding decoding and control circuits were added in the netlist of the circuit, which achieved fast input of test stimuli. Finally, an experiment using ISCA89 and IWLS2005 benchmark test circuits was performed. Experimental results were compared with those that used a serial input method of test stimuli. Results demonstrate that the proposed method can save approximately 37.5% and 43.7% of test time in average when the width of each group are 4 bits and 8 bits, respectively. The proposed method can decrease the clock cycles of scan testing significantly and shorten the scan testing time of the integrated circuit. Conclusions obtained in this study provide significant references for improving the scan testing method of digital integrated circuit. Keywords: Scan testing, Design for test, Test response, Test stimulus

Legalized routing is an essential part of PCB automatic routing. It solves the problem of wiring conflicts and obtains routing results that comply with the constraints of design rules. Traditional legalized routing problems mostly use trial backtracking methods, but with increasing design complexity and design rules, avoiding wiring conflicts between networks has become increasingly challenging. This paper proposes a legalized routing algorithm based on linear programming to obtain the optimal wiring trajectory under specified topological constraints. First, the corresponding routing model was established based on numerous routing rules, and a routing grid diagram was found using obstacles as grid points. Secondly, a global routing algorithm was used to obtain the estimated wiring path, and integer linear programming was used to realize the mathematical modeling of the legalized routing problem. Finally, a multi-line simultaneous routing strategy was used to design and implement a detailed routing algorithm, optimizing the routing results. We use C++ to complete the coding work and thoroughly test the PCB use cases of different sizes. The experimental results show that our algorithm still maintains a 100% routing success rate, good time performance, and excellent routing quality with large-scale use cases compared with the trial backtracking method.