A review on CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies. IC variables, namely, process, supply voltage, temperature, and noise sources that affect delay resolution through timing jitter are discussed. The design specifications of these delay elements are also discussed and compared for the common delay line circuits. As a result, the main findings of this paper are highlighting and discussing the followings: the most efficient high-resolution delay line techniques, the trade-off challenge found between CMOS delay lines designed using either analog or digitally-controlled delay elements, the trade-off challenge between delay resolution and delay range and the proposed solutions for this challenge, and how CMOS technology scaling can affect the performance of CMOS delay lines. Moreover, the current trends and efforts used in order to generate output delayed signal with low jitter in the sub-picosecond range are presented.

The performance of copper indium gallium diselenide (CIGS) thin film solar cell has been numerically simulated with different buffer and absorber layers thickness. The cell structure based on CIGS compound semiconductor as the absorber layer, indium sulfide as a buffer layer, un-doped (i) and n-doped zinc oxide as a window layer has been simulated using the simulation program called SCAPS-1D. This study aimed to find the optimum thickness of buffer and absorber layer for a CIGS thin film solar cells with indium sulfide buffer layer. It is found that the optimum thickness of the buffer layer is from 40nm to 50nm and for the absorber layer is in the range of 2000nm to 3000nm.