Karolis Kiela

Dr. Karolis Kiela


Research Focus & Metrics

Academic Career Length

11Years (2016-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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23 June 2020 in Applied Sciences
Verified
Journal Article
Open access
PDF file
KKKarolis Kiela
Karolis Kiela
Vaidotas BarzdenasVaidotas Barzdenas
Vaidotas Barzdenas
MJMarijan Jurgo
Marijan Jurgo
VMVytautas Macaitis
Vytautas Macaitis
JRJustas Rafanavicius
Justas Rafanavicius
Romualdas NavickasRomualdas Navickas
Romualdas Navickas
The intelligent transport system (ITS) has become one of the most globally researched topics with a lot of investment and development resources being dedicated into it due to its foreseen impact on the economic growth of the transport sector. Currently there are two main vehicle-to-everything (V2X) technologies, whose primary application is focused on ITS, backed up by the key players of various automotive, telecommunication and transport industries: dedicated short-range communications (DSRC) and cellular vehicle-to-everything (C-V2X), respectively based on IEEE 802.11p and 3GPP LTE/5G NR. While DSRC already has deployments, C-V2X is expected to see larger scale trails and deployments in 2020. In this work, the authors provide insight and review into two main V2X technologies, DSRC and C-V2X, their core parameters, shortcomings and limitations, and explore the need for integration of IoT-based technologies into modern ITS solutions. A comprehensive overview and analysis of currently commercially available V2X products, their sub-blocks and features is provided.

1 December 2016 in Journal of Electrical Engineering
Verified
Journal Article
Open access
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KKKarolis Kiela
Karolis Kiela
RNRomualdas Navickas
Romualdas Navickas
In this paper a tuning structure for a MOSFET?RC filters is presented. The proposed tuning structure is composed of switched resistor banks with voltage controlled transistors. The voltage controlled transistors use active feedback with extended control range for continuous filter parameter tuning, without degrading the total linearity performance of the filter. The proposed tuning structure is tested by implementing it in a second order low pass biquadratic filter cell in 65 nm CMOS technology. The designed filter has a highly reconfigurable response, ranging from Chebyshev to Bessel, a tuneable -3 dB bandwidth from 10 MHz to 100 MHz and can be used for multiple standard wireless solutions. Filter IIP3 performance is not degraded when the bandwidth is continuously tuned by 40 % with a 1 V pp input. The maximum power dissipation, including active feedback circuits, is 17.2 mW from a 1.2 V source when the filter is tuned to 100 MHz bandwidth.

19 March 2021 in Electronics
Verified
Journal Article
Open access
PDF file
KKKarolis Kiela
Karolis Kiela
MJMarijan Jurgo
Marijan Jurgo
VMVytautas Macaitis
Vytautas Macaitis
Romualdas NavickasRomualdas Navickas
Romualdas Navickas
This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.