The intelligent transport system (ITS) has become one of the most globally researched topics with a lot of investment and development resources being dedicated into it due to its foreseen impact on the economic growth of the transport sector. Currently there are two main vehicle-to-everything (V2X) technologies, whose primary application is focused on ITS, backed up by the key players of various automotive, telecommunication and transport industries: dedicated short-range communications (DSRC) and cellular vehicle-to-everything (C-V2X), respectively based on IEEE 802.11p and 3GPP LTE/5G NR. While DSRC already has deployments, C-V2X is expected to see larger scale trails and deployments in 2020. In this work, the authors provide insight and review into two main V2X technologies, DSRC and C-V2X, their core parameters, shortcomings and limitations, and explore the need for integration of IoT-based technologies into modern ITS solutions. A comprehensive overview and analysis of currently commercially available V2X products, their sub-blocks and features is provided.

In this work, an open Radio Access Network (RAN), compatible, scalable and highly flexible Software Defined Radio (SDR)-based Remote Radio Head (RRH) framework is proposed and designed. Such framework can be used to implement flexible wideband radio solutions, which can be deployed in any region, have common radio management features, and support various channel bandwidths. Moreover, it enables easier access for researchers to nonsimulated cellular networks, reduce system development time, provide test and measurement capabilities, and support existing and emerging wireless communication technologies. The performance of the proposed SDR framework is validated by creating a Network-in-a-Box (NIB) that can operate in multiband multicarrier 4G or 5G standalone (SA) configurations, with an output power of up to 33 dBm. Measurement results show, that the 4G and 5G NIB can achieve, respectively, up to 883 Mbps and 765 Mbps downlink data transfer speeds for a 100 MHz aggregated bandwidth. However, if six carriers are used in the 4G NIB, 1062 Mbps downlink data transfer speed can be achieved. When single user equipment (UE) is used, maximum uplink data transfer speed is 65.8 Mbps and 92.6 Mbps in case of 4G and 5G, respectively. The average packet latency in case of 5G is up to 45.1% lower than 4G. CPU load by the eNodeB and gNodeB is proportional to occupied bandwidth, but under the same aggregated DL bandwidth conditions, gNodeB load on the CPU is lower. Moreover, if only 1 UE is active, under same aggregated bandwidth conditions, the EPC CPU load is up to four times lower than the 5GC.

In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4mm×0.5mm of chip space and whole chip, including pads, occupies 1.5mm × 1.5mm area of silicon.

In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P_1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm² area of silicon and uses a 1.2 V supply.