The intelligent transport system (ITS) has become one of the most globally researched topics with a lot of investment and development resources being dedicated into it due to its foreseen impact on the economic growth of the transport sector. Currently there are two main vehicle-to-everything (V2X) technologies, whose primary application is focused on ITS, backed up by the key players of various automotive, telecommunication and transport industries: dedicated short-range communications (DSRC) and cellular vehicle-to-everything (C-V2X), respectively based on IEEE 802.11p and 3GPP LTE/5G NR. While DSRC already has deployments, C-V2X is expected to see larger scale trails and deployments in 2020. In this work, the authors provide insight and review into two main V2X technologies, DSRC and C-V2X, their core parameters, shortcomings and limitations, and explore the need for integration of IoT-based technologies into modern ITS solutions. A comprehensive overview and analysis of currently commercially available V2X products, their sub-blocks and features is provided.

Event-based cameras have increasingly become more commonplace in the commercial space as the performance of these cameras has also continued to increase to the degree where they can exponentially outperform their frame-based counterparts in many applications. However, instantiations of event-based cameras for depth estimation are sparse. After a short introduction detailing the salient differences and features of an event-based camera compared to that of a traditional, frame-based one, this work summarizes the published event-based methods and systems known to date. An analytical review of these methods and systems is performed, justifying the conclusions drawn. This work is concluded with insights and recommendations for further development in the field of event-based camera depth estimation.

Development of 5G networks requires a substantial increase to both spectral and power efficiency of transmitters. It is known that these two parameters are subjected to a mutual trade-off. To increase the linearity without losing power efficiency, linearization techniques are applied to power amplifiers. This paper aims to compare most popular linearization techniques to date and evaluate their applicability to upcoming 5G networks. The history of each respective linearization technique is followed by the main principle of operation, revealing advantages and disadvantages supported by concluding the latest research results. Three main groups of linearization methods currently known are feedforward, feedback, and predistortion, each with its own tradeoffs. Although digital predistortion seems to be the go-to method currently, other techniques with less research attention are still non-obsolete. A generalized discussion and a direct comparison of techniques analyzed are presented at the end of this paper. The article offers a systematic view on PA linearization problems which should be useful to researchers of this field. It is concluded that there are still a lot of problems that need to be addressed in every linearization technique in order to achieve 5G specifications.

The structure of the modern wireless network evolves rapidly and maturing 4G networks pave the way to next generation 5G communication. A tendency of shifting from traditional high-power tower-mounted base stations towards heterogeneous elements can be spotted, which is mainly caused by the increase of annual wireless users and devices connected to the network. The radio frequency (RF) power amplifier (PA) performance directly affects the efficiency of any transmitter, therefore, the emerging 5G cellular network requires new PA architectures with improved efficiency without sacrificing linearity. A review of the most promising reported RF PA architectures is presented in this article, emphasizing advantages, disadvantages and concluding with a quantitative comparison. The main scope of reviewed papers are PAs implemented in scalable complementary metal–oxide–semiconductor (CMOS) and SiGe BiCMOS processes with output powers suitable for portable wireless devices under 32 dBm (1.5 W) in the low- and high- 5G network frequency ranges.

The work presents a review of modern CMOS transimpedance amplifiers (TIAs) in the context of their application for low-cost optical time-domain reflectometry (OTDR). After introducing the basic principles behind the OTDR, the requirements for a suitable CMOS TIA are presented and discussed. A concise review of several basic TIA topologies is provided with a brief overview of their main properties. A detailed discussion is given on a representative set of approaches reported in the literature and the figure of merit (FOM) is introduced as a unified basis for performance comparison. Limitations of a single FOM as a basis for comparison are pointed out. Based on the provided discussion, some suggestions are made on the suitability of the TIA topologies for OTDR applications.

The modern era of technology contains a myriad of high-speed standards and proprietary serial digital protocols, which evolve alongside the microwave and RF realm. The increasing data rate push the requirements for hardware design, including modern printed circuit boards (PCB). One of these requirements for modern high-speed PCB interfaces are a homogenous track impedance all the way from the source to the load. Even though some high-speed interfaces don’t require any external components embedded into the interconnects, there are others which require either passive or active components—or both. Usually, component package land-pads are of fixed size, thus, if not addressed, they create discontinuities and degrade the transmitted signal. To solve this problem, impedance compensation techniques such as reference plane cut-out are employed for multiple case studies covering this topic. This paper presents an original method of finding the optimal cut-out size for the maximum characteristic impedance compensation in high-density multilayer PCB designs, which has been verified via theoretical estimation, computer simulation, and practical measurement results. Track-to-discontinuity ratios of 1:1.75, 1:2.5, and 1:5.0 were selected in order to resemble most practical design scenarios on a 6-layer standard thickness PCB. The measurements and simulations revealed that the compensated impedance saturation occurs at (150–250%) cut-out widths for a 50 Ω microstrip.