A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

In the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in standard 0.18 μm CMOS technology. The size of the pixel with 9-bit resolution is 21 μm × 21 μm. Measurements of the 128 × 128 pixel array confirm functionality of the proposed solution. CDS reduces dark FPN from 12 LSB (3%) to 0.8 LSB (0.2%) and light FPN from 14 LSB (3.7%) to 7 LSB (1.8%). Further reduction of the light FPN (to ~ 1 LSB) was achieved by compensating PRNU using massively parallel innovative digital multiplication which features good resolution (1/511), does not disturb CDS executed at the same time, and can be implemented within a small pixel area.

A high-frequency fully differential CMOS operational transconductance amplifier (OTA) is presented for continuous-time filter applications in the megahertz range. The proposed design technique combines a linear cross-coupled quad input stage with an enhanced folded-cascode circuit to increase the output resistance of the amplifier. SPICE simulations show that DC-gain enhancement can be obtained without significant bandwidth limitation. The two-input OTA developed is used in high-frequency tuneable filter design based on IFLF and LC ladder simulation structures. Simulated results of parameters and characteristics of the OTA and filters in a standard 1.2 µm CMOS process (MOSIS) are presented. A tuning circuit is also discussed.

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

The design of a linear, fully-balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with improved gain and very wide bandwidth is described. It uses a cross-coupled, two-differential-pair transconductor together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated DC-gain enhancement is obtained without any bandwidth limitation. SPICE simulation results show THD<1% at 1.9 Vp-p with dynamic range equal to 63 dB at a power consumption of 2.7 mW from a single 5-V supply. Application to a lowpass filter in the VHF range is presented as an example, assuming implementation in a standard 2 μm CMOS process (MOSIS). The cutoff frequency of the filter is tunable in the range of 8.3-50.0 MHz