The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.

5G NR (new radio) introduces the concept of massive MIMO (multiple-input multiple-output) technology, in which a larger number of antenna arrays are installed on the transceiver. Due to the increased number of antenna elements allocated close to each other (approximately at a distance of half a wavelength), mutual coupling becomes a serious problem leading to performance degradation of the MIMO communication system. In this communication, two different configurations of closely spaced antenna array elements are studied. In order to reduce the mutual coupling, a combination of a metamaterial-based frequency-selective surface (FSS), a metallic strip, and a slot element in the ground plane is examined. It is found that the proposed technique significantly suppresses mutual coupling from −12 dB to −25 dB. Both designs are fabricated and experimentally validated. The simulation results are in good agreement with the measurements. The proposed mutual coupling reduction technique may be suitable for massive MIMO systems in fifth-generation (5G) new radio applications.

The development of diffusion metasurfaces created new opportunities to elevate the stealthiness of combat aircraft. Despite the potential significance of metasurfaces, their rigorous design methodologies are still lacking, especially in the context of meticulous control over the scattering of electromagnetic (EM) waves through geometry parameter tuning. Another practical issue is insufficiency of the existing performance metrics, specifically, monostatic and bistatic evaluation of the reflectivity, especially at the design stage of metasurfaces. Both provide limited insight into the RCS reduction properties, with the latter being dependent on the selection of the planes over which the evaluation takes place. This paper introduces a novel performance metric for evaluating scattering characteristics of a metasurface, referred to as Normalized Partial Scattering Cross Section (NPSCS). The metric involves integration of the scattered energy over a specific solid angle, which allows for a comprehensive assessment of the structure performance in a format largely independent of the particular arrangement of the scattering lobes. We demonstrate the utility of the introduced metric using two specific metasurface architectures. In particular, we show that the integral-based metric can be used to discriminate between the various surface configurations (e.g., checkerboard versus random), which cannot be conclusively compared using traditional methods. Consequently, the proposed approach can be a useful tool in benchmarking radar cross section reduction performance of metamaterial-based, and other types of scattering structures.

A voltage unity-gain zero-offset CMOS amplifier with reduced gain error and increased PSRR (power supply rejection ratio) is proposed. The amplifier uses two feed mechanisms, negative feedback and supporting positive feedforward, to achieve low deviation from unit gain over the entire input range. The circuit, designed in a standard 180-nanometer 1.8-voltage CMOS process, is compared with two known buffers of similar topology, also designed in the same process. Simulations show that, with the same supply (1.8 V), power (1.2 mW), load (12 pF), bandwidth (50 MHz), and similar area (600 µm²), the proposed buffer achieves the lowest gain error (0.3%) and the highest PSRR (72 dB).

This paper presents a new implementation of the rank-order filter, which is established on a parallel-operated array of single-slope (SS) analog-to-digital converters (ADCs). The SS ADCs use an “on-the-ramp processing” technique, i.e., filtration is performed along with analog-to-digital conversion, so the final states of the converters represent a filtered image. A proof-of-concept 64 × 64 array of SS ADCs, integrated with MOS photogates, was fabricated using a standard 180 nm CMOS process. The measurement results demonstrate the full functionality of the novel filter concept, with image acquisition in both single-sampling and correlated-double-sampling (CDS) modes (CDS is digitally performed using ADCs). The experimental, massively parallel rank-order filter can process 650 frames per second with a power consumption of 4.81 mW.