A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

In the paper, a CMOS pixel has been proposed for imaging arrays with massively parallel image acquisition and simultaneous compensation of dark signal nonuniformity (DSNU) as well as photoresponse nonuniformity (PRNU). In our solution the pixel contains all necessary functional blocks: a photosensor and an analog-to-digital converter (ADC) with built-in correlated double sampling (CDS) integrated together. It is implemented in standard 0.18 μm CMOS technology. The size of the pixel with 9-bit resolution is 21 μm × 21 μm. Measurements of the 128 × 128 pixel array confirm functionality of the proposed solution. CDS reduces dark FPN from 12 LSB (3%) to 0.8 LSB (0.2%) and light FPN from 14 LSB (3.7%) to 7 LSB (1.8%). Further reduction of the light FPN (to ~ 1 LSB) was achieved by compensating PRNU using massively parallel innovative digital multiplication which features good resolution (1/511), does not disturb CDS executed at the same time, and can be implemented within a small pixel area.

An improved flipped voltage follower (FVF) and its application to a low-dropout (LDO) voltage regulator are presented. The proposed FVF improves most weaknesses of the classical one, namely its poor time response to the output current change from low to high value and poor stability for large capacitive load. The most important parameters of the modified FVF are analysed and described by analytical expressions. The parameters of the classical FVF and the improved one are compared and discussed. LDO regulator using the improved FVF is designed and implemented in AMS CMOS 0.35 µm technology. The measurement results of a test circuit show its relatively high current efficiency of 74 and 99.93% for output current 100 µA and 50 mA, respectively. The output voltage overshoot and undershoot are below 46 and 75 mV for output current change from 0.1 to 50 mA with the rise and fall times equal to 0.3 µs, and load capacitance 0–100 pF.

A new family of semi-analytical recursive convolution algorithms (SARC) suitable for efficient numerical analysis of linear systems in the time domain is presented. Consecutive output samples in the SARC algorithms are calculated with higher accuracy than in other recursive convolution algorithms. The main idea and outline of an error analysis are presented and some areas of the SARC algorithm's application are considered. The application of SARC algorithms to the synthesis of discrete-time filters is pointed out as a method of filter design.

The paper presents an operational transconductance amplifier (OTA) with low transconductance (0.62–6.28 nS) and low power consumption (28–270 nW) for the low-frequency analog front-ends in biomedical sensor interfaces. The proposed OTA implements an innovative, highly linear voltage-to-current converter based on the channel-length-modulation effect, which can be rail-to-rail driven. At 1-V supply and 1-V_pp asymmetrical input driving, the linearity error in the current-voltage characteristics is 1.5%, while the total harmonic distortion (THD) of the output current is 0.8%. For a symmetrical 2-V_pp input drive, the linearity error is 0.3%, whereas THD reaches 0.2%. The linearity is robust for the mismatch and the process-voltage-and-temperature (PVT) variations. The temperature drift of transconductance is 10 pS/°C. The prototype circuit was fabricated in 180-nanometer CMOS technology.