In this brief we present a novel, ultra-compact, True Random Number Generator (TRNG) architecture and its FPGA implementation. The proposed Latched Ring Oscillator (LRO) TRNG allows the generation of a TRNG bit from a single FPGA Slice. Despite its very compact structure, the proposed LRO-TRNG relies on both meta-stability and accumulated jitter as entropy sources, and exhibits very good results in terms of unpredictability and randomness. The proposed architecture has been implemented on Xilinx Spartan-6 devices and the TRNG performances have been extensively validated under supply voltage and temperature variations. Measurements results have shown that the LRO-TRNG exhibits an estimated entropy of about 7.99834 per bit (according to T8 test of the AIS-31) and a throughput of 0.76 Mbits/s with a 50MHz clock. A comparison against the state of the art shows that the proposed LRO-TRNG outperforms most of the previously published TRNGs, in terms of the ratio between throughput and FPGA resources usage.

This paper presents a True Random Number Generator (TRNG) exploiting latched-XOR (LX) gates and its implementation on a Xilinx Spartan 6 FPGA device. The proposed LX-TRNG aims at improving the Throughput (TP) of conventional ring oscillators (ROs) based TRNGs by combining the effect of latches metastability and ROs jitter. Measurements results have demonstrated that the generated bitstreams show very good randomness exhibiting a byte (bit) entropy of 7.9979 (0.9997), according to T8-test of AIS-31. The proposed TRNG has also been extensively tested under voltage and temperature variations showing very good robustness. In particular both NIST’s and AIS-31 tests are passed for all the considered supply voltage and temperature ranges. The FPGA implementation occupies only 9 Slices and, despite its compactness, it exhibits a throughput as high as 12.5 Mbit/s with a 50 MHz operating frequency. The computation of the figure of merit $FOM_E$ has shown the capability of the proposed TRNG to optimize the trade-off between hardware resources, bitstreams entropy and throughput, outperforming previous works.

In this work we introduce a novel lightweight FPGA compatible Physical Unclonable Function (PUF) primitive based on XOR gates. The proposed XOR-PUF is the most compact FPGA-compatible PUF ever presented in the literature, allowing the implementation of four PUF bits in a single Configurable Logic Block (CLB) and providing very good statistical performance. The architecture of the proposed PUF exploits two cross-coupled XOR gates which can be configured to behave as ring oscillators or SRAM cells. A 128-bit weak-PUF block based on the proposed XOR-PUF basic cell has been implemented on Xilinx Spartan-6 and Artix-7 devices and an extensive measurement campaign on 16 FPGA devices for each family has been carried out. Measurement results have shown that the proposed architecture and implementation are able to fit in just 64 Slices (32 CLBs) on both the Spartan-6 and Artix-7 devices without sacrificing statistical performance and guaranteeing a good robustness against supply voltage variations.

In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGA-compatible PUFs.

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 mm ² , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

For the design of inverter-based OTAs with differential input and single-ended output, the differential to single-ended (D2S) converter is a key building block. In fact, the performance of the D2S strongly affects the overall common-mode rejection ratio (CMRR) and input common-mode range (ICMR) of the whole OTA. In recent literature, inverter-based OTAs rely on a D2S topology based on an inverter driving another inverter with the input and output tight together which behaves as a “diode” connected device to implement a voltage gain approximately equal to –1. However, since this approach is based on the matching of the inverters, the performance of this D2S results sensitive to PVT variations if the bias point of the inverters is not properly stabilized. In this paper we present a novel topology of inverter-based D2S converter, exploiting an auxiliary, standard-cell-based, error amplifier and a local feedback loop. The proposed D2S, compared to the conventional one, exhibits higher CMRR, improved ICMR and better robustness with respect to PVT variations.We present also an ULV, standard-cell-based OTA, which exploits the proposed D2S converter and shows excellent performance figures of merit with low area footprint.