This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 mm ² , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

A novel technique for the digital background calibration of time-interleaved analog-to-digital converters is proposed. The technique corrects at the same time for both errors due to gain, offset and timing mismatches among the time-interleaved channels and errors due to nonlinearities in the channels, for instance due to capacitor mismatches in switched capacitor implementations. This feature, together with the use of the recursive least mean squares algorithm, makes the technique particularly fast (12 bits of accuracy can be achieved after about 4000 samples for a two-channel converter). The proposed calibration technique employs wideband differentiators, thus enabling digital background calibration of timing skews even with wideband input signals. Besides, undersampled differentiator filters are proposed, and it is shown that the technique is capable of calibrating undersampling converters by estimating the derivative of wideband input signals even outside the first Nyquist band.

The body‐driven variant of the gain‐boosting technique is here exploited to design a CMOS transconductance amplifier with minimum supply below 1 V. When compared with the conventional gain‐boosting technique, the proposed body‐driven approach reduces the minimum supply requirement by two thresholds in a rail‐to‐rail amplifier exploiting two complementary input stage topologies. Simulations using a 130‐nm process show that a 0.9‐V power supply is adequate for a single‐stage rail‐to‐rail amplifier providing a 56‐dB gain, which is 18 dB higher than that achieved by the same architecture but using the traditional cascoding approach. The main drawbacks are that the solution requires a twin‐tub process and an additional bias section. Copyright © 2008 John Wiley & Sons, Ltd.

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

An improvement of a standard fully differential class-AB symmetrical OTA topology is proposed in this paper to enhance the common-mode behavior. Common-mode behavior could be critical in fully differential class-AB OTAs, where the total current is not fixed and differential to common-mode conversion could therefore be present. A signal proportional to the input common-mode component is generated through a simple low-current auxiliary amplifier and used to modulate a bias voltage, achieving cancellation of the output common-mode component. Simulations in 40-nm CMOS technology show a net improvement of CMRR without affecting differential-mode behavior; the increase in area and power consumption is minimal, with a trade-off between power and settling time. Simulations of a sample-and-hold exploiting the proposed OTA are presented.

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.