This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) technology. The RFID logic circuit generates 16-bit code programmed in read-only memory. All circuits are implemented in a pseudo-CMOS logic style using transparent a-IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300-nm to 800-nm wavelength. The RFID logic chip generates Manchester-encoded 16-bit data with a 3.2-kHz clock frequency and consumes 170 μW at V_{\text{DD}}=6?\mathrm{V} . It employs 222 transistors and occupies a chip area of 5.85 mm².

This paper proposes a 0.25V rail-to-rail three stage OTA. The proposed OTA improves a DC gain by inserting an NMOS gate-driven amplifier into the conventional bulk-driven OTA. In addition, it uses an asymmetric self-cascode transistor and an indirect feedback compensation to enhance a DC gain and an unit-gain frequency. At the first stage, the bulk-driven amplifier has a rail-to-rail input, but it has a low DC gain due to a small transconductance. At the second stage, the NMOS gate-driven amplifier enhances the DC gain. At the last stage, the common-source amplifier drives an output load capacitor. The proposed OTA was fabricated using a 65nm CMOS process. Its area is 0.002mm. It consumes 0.026μW at the supply-voltage of 0.25V. The DC gain and unit-gain frequency are 70dB and 9.5kHz, respectively, with the phase margin of 88∘ at the load capacitance of 15pF.

Neuromorphic computing offers parallel data processing and low energy consumption and can be useful to replace conventional von Neumann computing. Memristors are two-terminal devices with varying conductance that can be used as synaptic arrays in hardware-based neuromorphic devices. In this research, we extensively investigate the analog symmetric multi-level switching characteristics of zinc tin oxide (ZTO)-based memristor devices for neuromorphic systems. A ZTO semiconductor layer is introduced between a complementary metal-oxide-semiconductor (CMOS) compatible Ni top electrode and a highly doped poly-Si bottom electrode. A variety of bio-realistic synaptic features are demonstrated, including long-term potentiation (LTP), long-term depression (LTD), and spike timing-dependent plasticity (STDP). The Ni/ZTO/Si device in which the adjustment of the number of states in conductance is realized by applying different pulse schemes is highly suitable for hardware-based neuromorphic applications. We evaluate the pattern recognition accuracy by implementing a system-level neural network simulation with ZTO-based memristor synapses. The density of states (DOS) and charge density plots reveal that oxygen vacancies in ZTO assist in generating resistive switching in the Ni/ZTO/Si device. The proposed ZTO-based memristor composed of metal-insulator-semiconductor (MIS) structure is expected to contribute to future neuromorphic applications through further studies.

We fabricated a Ni/SiO ₂ /Pt resistive random-access memory device referred to as a memristor, which demonstrates both volatile and non-volatile switching. A reversible transition between volatile and non-volatile switching is achieved by applying different current compliances (CCs). Volatile switching was observed when the CC is 50 nA, whereas volatile switching changed to non-volatile switching when the CC is 100 nA. The switching mechanism model can be explained by the formation and rupture of conducting filaments by electrochemical metallization effects, which are vital in resistive switching. We demonstrate a simple pulse measurement method for both switching behaviors. In a single Ni/SiO ₂ /Pt memristor device, short-term memory for volatile switching and a long-term memory synaptic function for non-volatile switching is observed under repeated stimuli. Owing to the distinctive characteristics of the Ni/SiO ₂ /Pt device, the short-term synaptic function, i.e. paired-pulse facilitation and depression for volatile switching, is successfully mimicked by the memristor. These electrical results indicate that the Ni/SiO ₂ /Pt memristor device with synaptic behavior has potential for use in brain-inspired computing systems.

This brief proposes a dc-dc buck converter using an analog coarse-fine self-tracking zero-current detection (ASTZCD) scheme. The AST-ZCD detects the zero-current by measuring the voltage level across a freewheeling transistor. It adjusts the nMOS turn-off time using an amplifier, capacitors, and current sources instead of large numbers of shift register bits and unit delay cells in the conventional digital self-tracking zerocurrent detection (DST-ZCD). It also reduces the zero-current self-tracking time by using coarse-fine current-sources when the output current transition is large. The proposed dc-dc buck converter was fabricated with a 0.18-μm CMOS process. The AST-ZCD reduces the area by 94%, the power consumption by 80%, and the zero-current self-tracking time by 82% compared to the DST-ZCD.

This paper proposes a low-power SRAM using bit-line charge-recycling for read and write operations. The charge-recycling SRAM (CR-SRAM) reduces the read and write powers by recycling the charge in bit lines. When N bit lines recycle their charges, the swing voltage and power of bit lines are reduced to 1/N and 1/N², respectively. The CR-SRAM utilizes hierarchical bit-line architecture to perform the charge-recycling without static noise margin degradation in memory cells. In the simulation, the CR-SRAM saves 17% read power and 84% write power compared with the conventional SRAM. A CR-SRAM chip with 4 K × 8 bits is implemented in a 0.13-μm CMOS process. It consumes 0.128-mW read power and 0.135-mW write power at f_CLK = 100 MHz and V_DD = 1.2 V.