This paper presents area optimization techniques for high-density spin-orbit torque magnetic random-access memories (SOT-MRAMs). Although SOT-MRAM has many desirable features of nonvolatility, high reliability and low write energy, it poses challenges to high-density memory implementation because of the use of two access transistors per cell. We first analyze the layout of the conventional SOT-MRAM bit-cell that includes two vertical metal lines, a bit-line and a source-line, limiting the horizontal dimension. We further propose two design techniques to reduce the horizontal dimension by decreasing the number of metal lines per cell without any performance overhead. Based on the fact that adjacent columns in a bit-interleaved array are not simultaneously accessed, the proposed techniques share a single source-line between two consecutive bit-cells in the same row. The simulation result shows that proposed techniques can achieve a bit-cell area reduction of 10–25% compared to the conventional SOT-MRAM. The comparison of our proposed designs with the standard spin-transfer torque MRAM shows 45% lower write energy, 84% lower read energy, and 2.3 × higher read-disturb margin.

In this paper, we present an energy-efficient real-time electrocardiogram (ECG) acquisition system that utilizes near-data processing for pre-diagnosis and controls the frequency of wireless communication to reduce power consumption. The system consists of a wearable ECG monitoring device, an Android-based smartphone application, and a database server, which mitigate the inconvenience of the periodical visit to the hospital. To maximize the battery lifetime, the prototype wearable device adopted algorithms with near-data processing to enable pre-diagnosis, which was verified using the MIT-BIH Arrhythmia database. Also, real-time acquisition is available by the data transmission between the wearable device and the smartphone utilizing Bluetooth Low Energy (BLE) when the device starts collecting the patient’s ECG data. The wearable device can not only acquire the raw ECG waveform data, but also provide an energy-saving option to send only feature data which is processed within the device for near-data pre-diagnosis. The overall power consumption of the device was reduced because the power consumption by communication was greatly reduced. Measured results verified that the feature data transmission with near-data processing can increase the battery lifetime by 15.9% compared to the conventional raw ECG data transmission.

We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECC used in memory controller outside of DRAM chip. We prove a sharp lower bound of aliasing probability and propose a simple method to come up with a code that meets the bound. By an experiment, we also demonstrate that a randomly chosen code is likely to have much more aliasings with overwhelmingly high probability.

This paper provides a comprehensive overview of the security vulnerability known as rowhammer in Dynamic Random-Access Memory (DRAM). While DRAM offers many desirable advantages, including low latency, high density, and cost-effectiveness, rowhammer vulnerability, first identified in 2014, poses a significant threat to computing systems. Rowhammer attacks involve repetitive access to specific DRAM rows, which can cause bit flips in neighboring rows, potentially compromising system credentials, integrity, and availability. The paper discusses the various stages of rowhammer attacks, explores existing attack techniques, and examines defense strategies. It also emphasizes the importance of understanding DRAM organization and the associated security challenges.

This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplications. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to the other alternatives. Moreover, our design delivers enhanced performance in image processing tasks, achieving up to a 4.84× increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency.

In this letter, we present a new structure of spin-orbit torque magnetic random access memory (SOT-MRAM) for area optimization. Based on the observation of SOT-MRAM layout that the metal line can be added in the horizontal direction without increasing the cell area, the proposed design optimizes the metal line routing direction as well as biasing conditions for read and write operations. Implemented with a 45-nm CMOS technology, the proposed design achieves cell area reduction of 42% (23%) compared with the conventional SOT-MRAM (STT-MRAM). The proposed design achieves 6.26x lower write power than STT-MRAM by taking advantage of high spin current injection efficiency. Also, owing to separate read and write current paths, the proposed design can optimize each path independently, resulting in 7.69x lower read power and 1.88x higher read-disturb margin in comparison to STT-MRAM that has a common path for read and write operations.